Clock domain crossing interface

A pulse sync circuit for transferring a synchronous input pulse from a source clock domain to a destination clock domain, comprising:

• a flip-flop for latching said input pulse in response to a transition of the source clock;
• a first clock sync module for transferring the latched input pulse from said flip-flop to said destination domain in response to a transition of the destination clock;
• a further clock sync circuit for transferring the latched pulse from said first clock sync module to said source domain in response to a transition of the source clock and applying said latched pulse to said flip-flop for resetting said flip-flop;
• and
• a gate for receiving said latched pulse from said flip-flop and the latched pulse from said further clock sync circuit and in response generating a busy signal.

A method of transferring data from a source clock domain to a destination clock domain, comprising:

• receiving a write control signal synchronized to said source clock domain and in response outputting a busy signal to said source clock domain and outputting said write control signal synchronized to said destination clock domain;
• latching write data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said write data from being latched in the event said busy signal is active so as not to corrupt previously write latched data;
• and
• receiving said write control signal from said pulse sync circuit and in response latching said write data on a transition of said destination clock.

A method of transferring a synchronous input pulse from a source clock domain to a destination clock domain, comprising:

• latching said input pulse in a flip-flop responsive to a transition of the source clock;
• transferring the latched input pulse from said flip-flop to said destination domain in response to a transition of the destination clock;
• receiving the latched pulse and outputting said pulse synchronized to a single cycle of the destination clock;
• transferring the latched pulse to said source domain in response to a transition of the source clock and applying said latched pulse to said flip-flop for resetting said flip-flop;
• and
• receiving said latched pulse from said flip-flop and the latched pulse transferred to said source domain and in response generating a busy signal.