Power budgeting between a processing core, a graphics core, and a bus on an integrated circuit when a limit is reached

A non-transitory storage medium including code, when executed, to cause a machine to perform the energy efficiency operations of:

• receiving a bus workload for a communication bus and a first processing element workload for a first processing element based on an integrated circuit reaching a limit, the integrated circuit including the communication bus and the first processing element, wherein the communication bus is to connect the first processing element with at least one other device of the integrated circuit;
• determining if the first processing element workload indicates the first processing element is a performance bottleneck;
• determining if the communication bus is able to accommodate the bus workload;
• capping a bus frequency of at least the communication bus and a frequency of a second processing element in response to determining the first processing element workload indicates the first processing element is the performance bottleneck and determining the communication bus is able to accommodate the bus workload;
• and
• increasing a previous cap on the bus frequency of at least the communication bus in response to determining the first processing element workload indicates the first processing element is the performance bottleneck and determining the communication bus is not able to accommodate the bus workload.

A method comprising:

• determining a processing workload activity for a central processor on a package;
• determining a graphics workload activity for a graphics processor on the package;
• determining a bus workload activity for a communication bus on the package;
• determining if the package has reached a thermal or power limit;
• communicating the processing workload activity, the graphics workload activity and the bus workload activity to a power controller of the package;
• and
• in response to determining the package has reached the thermal or power limit, dynamically balancing power between the central processor, the graphics processor, and the communication bus based on at least the graphics workload activity and the bus workload activity, including adjusting a maximum allowed frequency for the communication bus by a plurality of steps and adjusting a maximum allowed frequency for the central processor by a step.