US 8,898,439 B2 · Serial flash memory and address transmission method thereof

Abstract

A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.

Claims14

Dependent claims

An address transmission method of a serial flash memory, wherein the serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length, and a first memory address is completely received within an address time duration if the first memory space is addressed according to the first address length, so that data corresponding to the first memory address is initially outputted from a starting clock, wherein a waiting time duration exists between the address time duration and the starting clock, the address transmission method comprising the steps of:

receiving one portion of a second memory address within the address time duration if the second memory space is addressed according to the second address length, wherein address lengths of the first memory address and the second memory address are respectively equal to the first address length and the second address length;
and
receiving the other portion of the second memory address within a the waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.

A serial flash memory for selectively addressing a first memory space according to a first address length or addressing a second memory space according to a second address length longer than the first address length, the serial flash memory comprising:

a memory array;
and
an interface, wherein:
if the first memory space is addressed according to the first address length, the interface completely receives a first memory address within an address time duration, so that data corresponding to the first memory address is initially outputted from a starting clock, wherein a waiting time duration exists between the address time duration and the starting clock;
if the second memory space is addressed according to the second address length, the interface receives one portion of a second memory address within the address time duration, and receives the other portion of the second memory address within the waiting time duration, so that data of the memory array corresponding to the second memory address is initially outputted from the starting clock;
and
address lengths of the first memory address and the second memory address are respectively equal to the first address length and the second address length.

4 more elements

Dependencies are inferred from the claim text.

Serial flash memory and address transmission method thereof

Life of this patent

Serial flash memory and address transmission method thereof

Life of this patent

Abstract

Claims14