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US 8,898,438 B2Granted
Processor architecture for use in scheduling threads in response to communication activity
AssigneeXmos Ltd
InventorMichael David May
Life of this patent
Estimating the term…
Abstract
The invention provides a processor comprising an execution unit for executing multiple threads, each thread comprising a sequence of instructions and each thread being designated to handle activity from at least one specified source. The processor also comprises a thread scheduler for scheduling a plurality of threads to be executed by the execution unit, said scheduling being based on the respective activity handled by the threads; and a plurality of sets of registers connected to the execution unit. Each set of registers is arranged to store information representing a respective one of the plurality of threads, at least a part of the information being accessible by the execution unit for use in executing the respective thread when scheduled.
Claims46
A processor comprising:
- an execution unit for executing multiple threads and, for each of said multiple threads, respective hardware dedicated to that thread comprising a respective set of registers arranged to store information relating to that thread, each thread comprising a sequence of instructions, and each thread and its respective dedicated hardware being designated to handle respective communication activity from at least one respective specified communications source;
- and
- a thread scheduler for scheduling each of a plurality of said threads to be executed by the execution unit, wherein the scheduling of each respective one of said plurality of threads comprises suspending execution of the respective thread having been designated to handle the respective communication activity from the respective specified communications source, and resuming the respective thread based on the respective communication activity from the respective specified communications source designated to be handled by the respective thread;
- wherein at least a part of said information is accessible by the execution unit for use in executing the respective thread when scheduled;
- and
- wherein, for each of said threads, the respective hardware dedicated to that thread remains designated to handle the respective communication activity from the at least one respective specified communications source while that thread is suspended.
3 more elements
A method of managing the execution of a plurality of threads within a processor, the method comprising:
- in a plurality of sets of registers connected to an execution unit, storing in each set information relating to a respective one of said plurality of threads, each set of registers constituting respective hardware dedicated to that thread, each thread comprising a sequence of instructions, and each thread and its respective dedicated hardware being designated to handle respective communication activity from at least one respective specified communications source;
- scheduling each respective one of the plurality of threads to be executed by the execution unit, the scheduling of each respective thread comprising suspending the respective thread having been designated to handle the respective communication activity from the respective specified communications source, and resuming the respective thread based on the respective communication activity from the respective specified source designed to be handled by each thread;
- supplying at least a part of the information relating to a scheduled thread to the execution unit;
- and
- executing the threads in dependence on said supplied information;
- wherein, for each of said threads, the respective hardware dedicated to that thread remains designated to handle the respective communication activity from the at least one respective specified communications source while that thread is suspended.
3 more elements
A mobile terminal having a mobile applications processor, at least one peripheral device, and an interface processor connected between the mobile applications processor and the peripheral device, the interface processor comprising:
- an execution unit for executing multiple threads and, for each of said multiple threads, respective hardware dedicated to that thread comprising a respective set of thread registers arranged to store information relating to that thread, each thread comprising a sequence of instructions, and each thread and its respective dedicated hardware being designated to handle respective communication activity from at least one respective specified communications source;
- and
- a thread scheduler for scheduling each of a plurality of said threads to be executed by the execution unit, wherein the scheduling of each respective one of said plurality of threads comprises suspending the respective thread having been designate to handle the respective activity from the respective specified communications source, and resuming the respective thread based on the respective communication activity from the respective specified communications source designated to be handled by the respective thread;
- wherein at least a part of said information is accessible by the execution unit for use in executing the respective thread when scheduled;
- and
- wherein, for each of said threads, the respective hardware dedicated to that thread remains designated to handle the respective communication activity from the at least one respective specified communications source while that thread is suspended.
3 more elements
A processor comprising:
- execution means for executing multiple threads and, for each of said multiple threads, respective hardware dedicated to that thread comprising a respective set of thread registers arranged to store information relating to that thread, each thread comprising a sequence of instructions, and each thread and its respective dedicated hardware being designated to handle respective communication activity from at least one respective specified communications source;
- thread scheduling means for scheduling each of a plurality of said threads to be executed by the execution means, said scheduling of each respective one of said plurality of threads comprising suspending the respective thread having been designated to handle the respective communication activity from the respective specified communications source, and resuming the respective thread based on the respective communication activity from the respective specified communications source designated to be handled by the respective thread;
- and
- wherein at least a part of said information is accessible by the execution means for use in executing the respective thread when scheduled;
- and
- wherein, for each of said threads, the respective hardware dedicated to that thread remains designated to handle the respective communication activity from the at least one respective specified communications source while that thread is suspended.
3 more elements
Dependencies are inferred from the claim text.