US 8,898,437 B2 · Predecode repair cache for instructions that cross an instruction cache line

Abstract

A predecode repair cache is described in a processor capable of fetching and executing variable length instructions having instructions of at least two lengths which may be mixed in a program. An instruction cache is operable to store in an instruction cache line instructions having at least a first length and a second length, the second length longer than the first length. A predecoder is operable to predecode instructions fetched from the instruction cache that have invalid predecode information to form repaired predecode information. A predecode repair cache is operable to store the repaired predecode information associated with instructions of the second length that span across two cache lines in the instruction cache. Methods for filling the predecode repair cache and for executing an instruction that spans across two cache lines are also described.

Claims21

Dependent claims

A method of filling a predecode repair cache, the method comprising:

determining that a first portion of an instruction is stored in a first cache line of an instruction cache and a second portion of the instruction is stored in a next cache line of the instruction cache, wherein the instruction has corresponding predecode information;
in response to determining that the instruction spans the first cache line and the next cache line, generating repaired predecode information;
storing the repaired predecode information at the predecode repair cache utilizing an address associated with the instruction;
and
selecting between the repaired predecode information stored at the predecode repair cache and the predecode information.

2 more elements

A method of executing instructions, the method comprising:

fetching a first portion of an instruction that spans across two cache lines, the first portion of the instruction stored in a first cache line in an instruction cache, the instruction having corresponding predecode bits;
fetching repaired predecode information associated with the instruction from a predecode repair cache that is separate from the instruction cache, wherein the repaired predecode information is generated based on a determination that the first portion of the instruction is stored in the first cache line and a second portion of the instruction is stored in a next cache line;
fetching the second portion of the instruction stored in the next cache line following the first cache line, wherein fetching the second portion of the instruction includes selecting between the repaired predecode information stored at the predecode repair cache and the predecode bits;
and
executing the instruction in response to the repaired predecode information.

2 more elements

An apparatus for utilizing a predecode repair cache, the apparatus comprising:

an instruction cache operable to store instructions having at least a first length and a second length in an instruction cache line, the second length being longer than the first length, wherein the instruction has corresponding predecode information;
a predecoder operable to predecode an instruction fetched from the instruction cache to form repaired predecode information based on a determination that a first portion of the instruction is stored in a first cache line of the instruction cache and a second portion of the instruction is stored in a next cache line of the instruction cache;
a predecode repair cache operable to store the repaired predecode information associated with the instruction;
and
control logic operable to select between the repaired predecode information stored at the predecode repair cache and the predecode information.

2 more elements

Dependencies are inferred from the claim text.

Predecode repair cache for instructions that cross an instruction cache line

Life of this patent

Predecode repair cache for instructions that cross an instruction cache line

Life of this patent

Abstract

Claims21