US 8,898,435 B2Granted

Optimizing system throughput by automatically altering thread co-execution based on operating system directives

AssigneeLenovo Enterprise Solutions (Singapore) Pte. Ltd.

InventorsAmit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan

Life of this patent

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Abstract

A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.

Claims7

Dependent claims

A method for optimizing program instruction execution throughput in a processor apparatus having at least one central processing unit core (CPU), comprising:

implementing a simultaneous multithreaded (SMT) operational mode in said CPU wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing a cache memory resource within said CPU;
implementing an autothread (AT) operational mode in said CPU;
determining as part of said AT operational mode (1) whether there is a resource conflict between said hardware threads, and (2) whether said resource conflict undermines instruction execution throughput;
and
if said determining detects a resource conflict that undermines instruction execution throughput, adjusting relative instruction execution rates of said hardware threads in said CPU based on relative priorities of said software threads specified to said processor apparatus by a software scheduling entity.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/093,340Filed 29 Nov 2013 · continuation
Priority: 11 Nov 2011
Published: US 2014/0089637 A127 Mar 2014
Granted: 25 Nov 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/52
Multiprogramming arrangements: program synchronisation; Mutual exclusion, e.g. by means of semaphores
G06F 11/3409
Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of…:…
G06F 11/3466
Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of…:…

Family

Application13/294,244Parent of this continuation · filed 11 Nov 2011
US 2014/0089637 A1Pre-grant publication · published 27 Mar 2014
US 2013/0124826 A1Published application
US 8,898,434 B2Related patent
US 8,898,435 B2This patent

From the US filing history. Foreign family members aren’t listed.