Fault handling in address translation transactions

A method of handling faults within address translation circuitry in a data processing apparatus, the data processing apparatus comprising:

• a processor for processing a stream of instructions;
• a hierarchical memory system comprising a cache a memory and cache management circuitry;
• said processor identifying storage locations using virtual addresses and said memory system storing data using physical addresses, said memory being configured to store tables comprising virtual to physical address translations, said cache being configured to store a subset of said virtual to physical address translations, said cache management circuitry being configured to control transactions received from said processor requesting virtual address to physical address translations;
• said method comprising the steps of:
• identifying where a faulting transaction has occurred and whether said faulting transaction has a transaction stall or transaction terminate fault;
• responding to identification of said faulting transaction and to said faulting transaction having a transaction terminate fault by invalidating all address translations in said cache that relate to said context of said faulting transaction;
• and
• responding to identification of said faulting transaction and to said faulting transaction having a transaction stall fault by setting a stall indicator associated with all address translations in said cache that relate to said context of said faulting transaction.

A data processing apparatus comprising:

• means for processing a stream of instructions;
• a hierarchical memory system comprising a means for caching, a memory and means for cache management;
• said means for processing configured to identify storage locations using virtual addresses and said memory system storing data using physical addresses, said memory being configured to store tables comprising virtual to physical address translations, said means for caching being for storing a subset of said virtual to physical address translations, said means for cache management being for controlling transactions received from said means for processing requesting virtual address to physical address translations;
• wherein
• said data processing apparatus is configured to identify where a faulting transaction has occurred during execution of a context and whether said faulting transaction has a transaction stall or transaction terminate fault;
• said means for cache management is configured to:
• respond to identification of said faulting transaction and to said faulting transaction having a transaction terminate fault by invalidating all address translations in said means for caching that relate to said context of said faulting transaction such that a valid bit associated with each entry in said means for caching is set to invalid for said address translations, invalid entries being available for update and not forming part of any lookup in said means for caching;
• and
• respond to identification of said faulting transaction and to said faulting transaction having a transaction stall fault by setting a stall indicator associated with all address translations in said means for caching that relate to said context of said faulting transaction.