Memory address translation
AssigneeMicron Technology, Inc.
InventorsTroy A. Manning, Martin L. Culley, Troy D. Larsen
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsTroy A. Manning, Martin L. Culley, Troy D. Larsen
Estimating the term…
The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
A memory device, comprising:
A memory device, comprising:
A memory device, comprising:
A method of operating a memory device, comprising:
A method of operating a memory device, comprising:
Dependencies are inferred from the claim text.