Methods and apparatuses for improving speculation success in processors
AssigneeOracle America, Inc.
InventorsChaiyasit Manovit, Paul Nicholas Loewenstein
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.
Claims20
A method of executing instructions in a computer system, the method comprising the acts of:
- speculatively executing a first thread of a program code while a second thread of the program code is executing;
- determining if a load request from the first thread is serviceable from a cache line within a cache;
- in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line;
- determining if the cache line has been evicted;
- and
- in the event that the cache line is evicted, allowing speculative execution of the first thread to continue;
- and
- committing changes to one or more lines of memory that occur in response to the speculative execution, including committing changes to the cache line that occur after the cache line has been evicted.
A computer system comprising:
- a plurality of processing cores, each capable of executing at least one thread of program code, wherein each of the cores within the plurality of processing cores comprises:
- a plurality of register files;
- and
- a cache coupled to the plurality of register files, wherein each cache line within the cache further comprises a first indicator bit;
- wherein a first core within the plurality of processing cores executes a first thread of the program code out-of-order code while a second core within the plurality of processing cores executes a second thread of program code;
- and
- wherein, in the event that a load request from the first thread hits to a cache line with the first indicator bit set, and that hit cache line is later evicted from the cache, the first thread continues to execute the program code out-of-order and changes to one or more lines of memory that occur in response to the out-of-order execution are committed, including changes to the cache line that occur after the cache line has been evicted.
A non-transitory storage medium comprising instructions capable of being executed by a computer system, the instructions comprising the acts of:
- speculatively executing a first thread of a program code while a second thread of the program code is executing;
- determining if a load request from the first thread is serviceable from a cache line within a cache;
- in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line;
- determining if the cache line has been evicted;
- and
- in the event that the cache line is evicted, allowing speculative execution of the first thread to continue and committing changes to one or more lines of memory that occur in response to the speculative execution, including committing changes to the cache line that occur after the cache line has been evicted.
Dependencies are inferred from the claim text.