Memory and process sharing across multiple chipsets via input/output with virtualization

#In general, embodiments of the present invention provide a multiple chipset circuit design. Specifically, embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization.

#With increasing demands on functionality and performance as well as improved fabrication techniques, newer generations of processors and other integrated circuits have significantly higher levels of integration than their predecessors. Additionally, in some instances, different market segments may exist for compatible versions of processors and other types of integrated circuits having price and performance characteristics specific to a particular market segment. However, given the complexity and expense of designing a single version of a processor or other integrated circuit having a large transistor count, it may be impractical to separately design and manufacture a processor for each of several different market segments.

#These issues may be compounded as mobile devices become more pervasive. Specifically, mobile systems typically suffer from power leakage and consumption of their internal circuits. Currently, low-power circuits are based on conventional design schemes. Moreover, mobile multi-core processor and multi-chip systems require a fundamentally different design approach for cores and on-chip memories. Under such configurations, multiple chipsets may be utilized in a single system, with each chipset requiring separate memory resources. Such scattered memory resources may lead to extensive power leakage.

#These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:

#FIG. 1 depicts a diagram of chipset system according to an embodiment of the present invention.

#FIG. 2 depicts a diagram of a chipset system in a first mode according to an embodiment of the present invention.

#The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.

#Illustrative embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

#The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term “set” is intended to mean a quantity of at least one. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.