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US 8,898,390 B2Granted
Scheduling workloads based on cache asymmetry
AssigneeIntel Corporation
InventorsXiaowei Jiang, Li Zhao, Ravishankar Iyer
Life of this patent
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Abstract
In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.
Claims18
An apparatus comprising:
- a processor including a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache, the first and second caches asymmetric caches of a common cache level, wherein a scheduler is to schedule a plurality of threads to the first and second cores based at least in part on cache performance information obtained during a training phase of the plurality of threads on the asymmetric caches, and a predictor to predict cache performance of a first thread on the second cache during the training phase of the first thread on the first core using the first cache.
A method comprising:
- initiating a thread on a first core of a processor;
- measuring cache performance of the thread on a first cache used by the thread and predicting cache performance of the thread on a second cache unused by the thread, the first and second caches of asymmetric size, and storing cache performance information regarding the cache performance in a storage;
- determining a thread-to-core mapping based on the cache performance information, including computing a sum for each of a plurality of possible schedules for the thread, a second thread, and a third thread on the first core, a second core associated with the second cache, and a third core associated with the second cache;
- and
- scheduling the thread to the first core or the second core based on the thread-to-core mapping.
2 more elements
A processor comprising:
- a first cache;
- a second cache;
- a first core associated with the first cache;
- a second core associated with the second cache, the first and second caches asymmetric caches of a common cache level;
- and
- a scheduler to schedule a plurality of threads to the first and second cores based at least in part on cache performance information obtained during a training phase of the plurality of threads on the asymmetric caches, wherein when the first and second caches are private caches, the scheduler is to calculate a first sum of miss rate values for use of the first cache by a first thread and use of the second cache by a second thread, and to calculate a second sum of miss rate values for use of the second cache by the first thread and use of the first cache by the second thread, and to schedule the first and second threads according to the smaller sum.
3 more elements
Dependencies are inferred from the claim text.