Flash memory device and method for managing flash memory device

A method for managing a flash memory device coupled to a host, wherein the flash memory device comprises a flash memory for storing data and a controller for managing data access of the flash memory, receiving data to be stored in the flash memory device from the host for the host to store the data in the flash memory device and transmitting the data read out from the flash memory device to the host for the host to read the data from the flash memory device, comprising:

• during a write operation, receiving data from the host and writing the data to a single level memory module of the flash memory, wherein the single level memory module comprises a first data bus and at least one single level cell (SLC) flash memory, the data is written into the SLC flash memory according to a first data order, and each memory cell of the SLC flash memory stores one bit of data, and wherein the flash memory further comprises a multi level memory module, the multi level memory module comprises a second data bus coupled to the first data bus and at least one multi level cell (MLC) flash memory, and each memory cell of the MLC flash memory stores more than one bit of data;
• transmitting the data stored in the SLC flash memory to the multi level memory module according to a second data order through the first and second data buses coupled therebetween without passing the data through the controller, so as to write the data into the MLC flash memory, and
• during a read operation, reading the data from the multi level memory module according to the first data order,
• wherein the first data order is different from the second data order,
• wherein the step of writing the data to the single level memory module further comprises:
• writing the data into the flash memory according to an error correction code, and
• wherein the step of reading the data from the multi level memory device further comprises:
• decoding the data according to the error correction code;
• when a number of error bits detected in a sub-page of a physical page is determined to have exceeded a correctable error bit number during a decoding process, deriving one or more memory cells of the physical page that has/have the possibility of having the error bit(s) occurring therein according to content of the memory cell(s) in adjacent physical page(s), wherein the one or more memory cells of the physical page that has/have the possibility of having the error bit(s) occurring therein is/are derived when there is a memory cell that is programmed to a logical state that has great influence on the other stored logical states exists in the adjacent physical page(s);
• predicting original content stored in the one or more memory cells according to the content stored in the adjacent memory cell(s);
• and
• performing error correction code decoding of the physical page again according the predicted original content.