Data storage method for flash memory, and flash memory controller and flash memory storage system using the same

A flash memory controller, for storing data into a flash memory chip, wherein the flash memory chip has a plurality of physical blocks and each of the physical block has a plurality of physical addresses, the physical addresses comprise at least one fast physical address and at least one slow physical address, and a speed of writing data into the at least one fast physical address is faster than a speed of writing data into the at least one slow physical address, the flash memory controller comprising:

• a microprocessor unit;
• a flash memory interface unit, coupled to the microprocessor unit, and configured to couple to the flash memory chip;
• a host interface unit, coupled to the microprocessor unit, and configured to couple to a host system;
• and
• a memory management unit, coupled to the microprocessor unit,
• wherein the memory management unit configures a plurality of logical addresses, wherein each of the logical addresses is mapped to one of the physical addresses,
• wherein the memory management unit monitors a usage rate of the physical addresses of at least two of the physical blocks and determines whether the usage rate of the physical addresses of at least two of the physical blocks is larger than a usage rate threshold value, wherein the usage rate is calculated based on a ratio of the physical addresses containing valid data to all the physical addresses of at least two of the physical blocks,
• wherein the memory management unit stores the data into the flash memory chip by using a fast mode when the usage rate of the physical addresses of at least two of the physical blocks is not larger than the usage rate threshold value, wherein the memory management unit only uses the at least one fast physical address to store the data in the fast mode.

A flash memory storage system, comprising:

• a flash memory chip, having a plurality of physical blocks and each of the physical block has a plurality of physical addresses, wherein the physical addresses comprise at least one fast physical address and at least one slow physical address, and a speed of writing data into the at least one fast physical address is faster than a speed of writing data into the at least one slow physical address;
• a connector, configured to couple to a host system;
• and
• a flash memory controller, coupled to the flash memory chip and the connector,
• wherein the flash memory controller configures a plurality of logical addresses, wherein each of the logical addresses is mapped to one of the physical addresses,
• wherein the flash memory controller monitors a usage rate of the physical addresses of at least two of the physical blocks and determines whether the usage rate is larger than a usage rate threshold value, wherein the usage rate is calculated based on a ratio of the physical addresses containing valid data to all the physical addresses of at least two of the physical blocks,
• wherein the flash memory controller stores data into the flash memory chip by using a fast mode when the usage rate of the physical addresses of at least two of the physical blocks is not larger than the usage rate threshold value, wherein the flash memory controller only uses the at least one fast physical address to store the data in the fast mode.