Redriven/retimed registered dual inline memory module

A DIMM, comprising:

• a plurality of dynamic random access memory (DRAM) chips, each DRAM chip having a plurality of data input/output (D/Q) terminals, each of said D/Q terminals having an associated load such that said DRAM chips present a plurality of loads;
• a system memory bus comprising a bidirectional parallel data bus provided to transfer data between a memory controller and the DRAM chips;
• and
• a data redriving/retiming circuit coupled between the system memory bus and the plurality of D/Q terminals such that data is written from the system memory bus to selected DRAM chips in parallel and is read from the selected DRAM chips and provided to the system memory bus in parallel via the data redriving/retiming circuit,
• wherein the data redriving/retiming circuits provide isolation between said system memory bus and the D/Q terminals of the DRAM chips, thereby isolating said system memory bus from said plurality of loads associated with said plurality of DRAM chips;
• wherein the data redriving/retiming circuits comprise:
• a first register to store data received via the system memory bus for writing into the plurality of DRAM chips;
• a second register to store data read from the plurality of DRAM chips for output to the system memory bus, wherein each of said first and second registers has an input and an output;
• a first buffer arranged to receive and buffer said data stored in said first register;
• and
• a second buffer arranged to receive and buffer said data stored in said second register, wherein each of said first and second buffers has an input and an output, the output of said first register connected to the input of said first buffer, the output of said first buffer connected to the input of said second register, the output of said second register connected to the input of said second buffer, and the output of said second buffer connected to the input of said first register.

A method for operating a computing device, the computing device including a CPU and a DIMM, the DIMM comprising a plurality of dynamic random access memory (DRAM) devices, each of the DRAM devices having a plurality of data input/output (D/Q) terminals, each of said D/Q terminals having an associated load, the method comprising:

• writing first data in parallel from a system memory bus to selected DRAM chips, the system memory bus being characterized as a bidirectional parallel data bus to transfer data between a memory controller and the DRAM devices;
• reading second data in parallel from selected DRAM chips and providing the second data to the system memory bus;
• and
• isolating, using a data redriving/retiming circuit, the system memory bus from each of the loads associated with said D/Q terminals during either the writing or the reading, such that the system memory bus is subjected to a predetermined load using the data redriving/retiming circuit independent of a quantity of the DRAM devices in the plurality of DRAM devices;
• wherein the data redriving/retiming circuit comprises:
• a first register to store data received via the system memory bus for writing into the plurality of DRAM chips;
• a second register to store data read from the plurality of DRAM chips for output to the system memory bus, wherein each of said first and second registers has an input and an output;
• a first buffer arranged to receive and buffer said data stored in said first register;
• and
• a second buffer arranged to receive and buffer said data stored in said second register, wherein each of said first and second buffers has an input and an output, the output of said first register connected to the input of said first buffer, the output of said first buffer connected to the input of said second register, the output of said second register connected to the input of said second buffer, and the output of said second buffer connected to the input of said first register.