Combined power and input/output line
AssigneeMicrochip Technology Incorporated
InventorsJoseph Julicher, Pieter Schieke, Vivien Delport
Life of this patent
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Abstract
An electronic device including a host system including a source; and a target system operably coupled to the host system via a combined power I/O line; wherein the target system includes a pass transistor and a switching system cooperative to allow the source to charge a power supply capacitor on the target system via the combined power I/O line in a first mode and alternately charge and discharge the power supply capacitor during a communication via the combined power I/O line in a second mode, wherein the alternately charging and discharging is in synchronization with said communication.
Claims23
A combined power and input/output system, comprising:
- a host system;
- a target system operably coupled to the host system via a combined power and I/O line;
- wherein the host system is configured to charge a power supply capacitor in the target system in a first mode via the combined power and I/O line and communicate via the combined power and I/O line in a second mode,
- wherein the target system comprises a pass transistor interposed between the host system and the power supply capacitor on the combined power and I/O line,
- a switching system operable in cooperation with the pass transistor to charge and discharge the power supply capacitor during communication in the second mode,
- wherein during an input phase of the second mode in which data is transmitted from the host to the target system, the pass transistor is asserted for a predetermined period after a rising edge of a data bit and wherein during an output phase of the second mode in which data is transmitted from the target system to the host system, the pass transistor is asserted for an entirety of a high portion of a data bit.
A method for providing power and I/O on a single line, comprising:
- driving a combined I/O power line to charge a power supply capacitor in a first mode;
- alternately connecting and disconnecting a pass transistor to charge and discharge the power supply capacitor during a communication over the combined I/O power line in a second mode, wherein during data input, the pass transistor is asserted so as to charge the power supply capacitor responsive to a rising edge of a data bit, and wherein during data output, the pass transistor is asserted for an entire high portion of a data bit.
An electronic device, comprising:
- a host system;
- a target system operably coupled to the host system via a combined power I/O line;
- wherein the target system includes a pass transistor and a switching system cooperative to allow the host system to charge a power supply capacitor on the target system via the combined power I/O line in a first mode and alternately charge and discharge the power supply capacitor during a communication via the combined power I/O line in a second mode, wherein the alternately charging and discharging is in synchronization with said communication, wherein during data input of the second mode, the pass transistor is asserted so as to charge the power supply capacitor responsive to a rising edge of a data bit and wherein during data output of the second mode, the pass transistor is asserted for an entire high portion of a data bit.
Dependencies are inferred from the claim text.