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US 8,898,350 B2Granted
Multi-bus architecture for mass storage system-on-chip controllers
AssigneeSpanison LLC
InventorRavindra K. Kanade
Life of this patent
Estimating the term…
Abstract
Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a controller second bus can be designated for the transfer of data to the mass storage devices. By architecting the memory controller component with two buses, this innovation can provide a higher data throughput than conventional memory controllers.
Claims20
A system that transfers data between at least one host component and at least one memory component, comprising:
- a memory controller, wherein the memory controller comprises:
- a controller processor,
- a controller first bus that is configured to transfer at least instruction code for the controller processor, wherein at least a portion of the instruction code is used to perform one or more memory-maintenance operations on one or more memory cells in the at least one memory component, and wherein the controller first bus is communicatively connected to the at least one host component and the at least one memory component, and
- a controller second bus that is configured to transfer at least a portion of data associated with a data transaction between the at least one host component and the at least one memory component,
- wherein the controller second bus is communicatively connected to the at least one host component and the at least one memory component,
- wherein transfer of the at least the portion of the data via the controller second bus is independent from transfer of the instruction code via the controller first bus,
- wherein the controller processor is further configured to determine whether the controller second bus is able to transfer all of the data associated with the data transaction, and, in response to the controller processor determining that not all of the data associated with the data transaction is able to be transferred via the controller second bus, the controller processor facilitates transfer of a first portion of the data associated with the data transaction between the at least one host component and the at least one memory component and the transfer of the instruction code via the controller first bus at a same time as transfer of a second portion of the data associated with the data transaction via the controller second bus, to transfer the data associated with the data transaction simultaneously with the performance of the one or more memory-maintenance operations on the one or more memory cells, and
- wherein, in connection with the data transaction, the controller processor is further configured to facilitate determining whether the controller second bus is available to perform another data transaction to facilitate determining whether the controller second bus is to be configured to perform the other data transaction;
- a direct memory access (DMA) component that is connected to the controller second bus, wherein the controller processor is further configured to configure the direct memory access component to control the transfer of the at least the portion of the data via the controller second bus based at least in part on at least one other portion of the instruction code, wherein the controller first bus is configured to transfer the at least the portion of the instruction code to perform the one or more memory-maintenance operations on the one or more memory cells at the same time the controller second bus transfers the at least the portion of the data, and wherein the DMA component controls the transfer of the at least the portion of the data associated with the data transaction between the at least one host component and the at least one memory component via the controller second bus such that the transfer of the at least the portion of the data is performed without interruption;
- and
- the at least one memory component is communicatively coupled to the memory controller.
8 more elements
A method that facilitates controlling data transfers, comprising:
- transferring instruction code to a controller processor via a controller first bus that is communicatively connected to a host component and a memory, wherein at least a portion of the instruction code is used to perform one or more memory-maintenance operations on one or more memory locations in the memory;
- determining whether a controller second bus is able to transfer all of the data associated with a data transfer between the host component and the memory;
- configuring a direct memory access (DMA) component to control at least a portion of the data transfer via the controller second bus based at least in part on at least one other portion of the instruction code at least in response to determining that the controller second bus is able to transfer all of the data associated with the data transfer;
- transferring at least a portion of the data associated with the data transfer via the controller second bus based at least in part on the at least one other portion of the instruction code, wherein the controller second bus is independent from the controller first bus;
- transferring at least one other portion of the data associated with the data transfer, in addition to the instruction code, via the controller first bus in response to determining that the controller second bus is not able to transfer all of the data associated with the data transfer;
- controlling the transfer of the at least the portion of the data associated with the data transfer via the controller second bus to transfer the at least the portion of the data without interruption;
- performing the one or more memory-maintenance operations on the one or more memory locations via the controller first bus simultaneously with the transferring of the at least the portion of that data via the controller second bus;
- in connection with the data transfer, facilitating determining whether the controller second bus is available to perform another data transfer between the host component and the memory to facilitate determining whether the controller second bus is to be configured to perform the other data transfer;
- and
- scheduling a reduction of power of the controller second bus to occur at the completion time to facilitate reducing power consumption by the controller second bus during a time period the controller second bus is not transferring data.
7 more elements
A system for controlling data, comprising:
- means for determining whether a controller second bus is able to transfer all data associated with the data transaction between a host component and a memory;
- means for transferring at least one of a first set of data associated with the data transaction or a first set of instruction code via a controller first bus that is connected to the host component and the memory, wherein at least a portion of the first set of instruction code is used to perform at least one memory-maintenance operation on at least one memory cell in the memory;
- means for configuring the controller second bus with a processor subsystem that executes at least one other portion of the first set of instruction code to transfer at least one of the first set of data, a second set of data associated with the data transaction, or a second set of instruction code, wherein the processor subsystem is communicatively coupled to the controller first bus;
- means for performing the at least one memory-maintenance operation on the at least one memory cell based at least in part on the transferring of the at least the portion of the first set of instruction code via the controller first bus;
- means for transferring the at least one of the first set of data, the second set of data or the second set of instruction code via the controller second bus, wherein the transferring of the at least one of the first set of data or the first set of instruction code via the controller first bus occurs at a same time as the transferring of the at least one of the first set of data, the second set of data or the second set of instruction code via the controller second bus, wherein the first set of data and the second set of data are transferred via the controller second bus in response to determining that the controller second bus is able to transfer all of the data associated with the data transaction, and wherein the first set of data is transferred via the controller first bus in response to determining that the controller second bus is not able to transfer all of the data associated with the data transaction, wherein the transferring of the first set of data or the second set of data is performed simultaneously with the performing of the at least one memory-maintenance operation on the at least one memory cell;
- means for controlling the transferring of the first set of data or the second set of data via the controller second bus to transfer the first set of data or the second set of data without interruption;
- means for determining whether the controller second bus is available to perform another data transaction between the host component and the memory, in relation to a status of the data transaction, to facilitate determining whether the controller second bus is to be configured to perform the other data transfer;
- and
- means for scheduling a reduction of power of the controller second bus to occur at the completion time to facilitate reducing power consumption by the controller second bus during a time period the controller second bus is not transferring data.
6 more elements
Dependencies are inferred from the claim text.