US 8,898,246 B2 · Communication among partitioned devices

Abstract

A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

Claims38

Dependent claims

A computing device having partitions, wherein at least one partition comprises:

at least one cell;
at least one register that in normal use of the device is accessible to other partitions and capable of defining an accessible address area;
and
the at least one partition is arranged to permit other partitions to access at least one accessible address area defined by the at least one register and to deny other partitions access to address areas other than the at least one accessible address area;
wherein the at least one partition comprises information associated with the at least one register and specifying which other partitions are permitted to access the accessible address area identified by the at least one register;
and
wherein the at least one register comprises a sharing set register within the at least one partition containing the information specifying which other partitions are permitted to access the accessible address area.

4 more elements

A device for use as a partition in a partitioned multiprocessor system, the device comprising at least a processor, addressable memory, and at least one register defining a local address area, the at least one register including at least one sharing set register specifying which of a plurality of other partitions are permitted to read the at least one accessible local address area, and being arrangeable in use to:

make the at least one register readable to other partitions;
make at least one accessible local address area defined by the at least one register readable to other partitions;
maintain address areas other than the at least one accessible local address area and prevent access to those other address areas from other partitions;
maintain information giving the location of at least one remote register in another partition;
obtain from the at least one remote register the address of at least one accessible remote address area in the other partition accessible to the processor;
read and respond to data in the at least one accessible remote address area;
and
place data for a processor in the other partition in the at least one accessible local address area.

5 more elements

Dependencies are inferred from the claim text.

Communication among partitioned devices

Life of this patent

Communication among partitioned devices

Life of this patent

Abstract

Claims38