On-chip packet cut-through

A line card for avoiding memory bandwidth utilization during packet processing, the line card comprising:

• an ingress port to receive a plurality of packets;
• an egress port to transmit a plurality of packets;
• an off-chip packet store to store one or more off-chip packet queues, each off-chip packet queue to store one or more of the received packets prior to transmitting the packets to the plurality of egress ports;
• and
• a packet processing core to process the plurality of received packets, the packet processing core comprising:
• an on-chip packet store to store one or more on-chip packet queues, each on-chip packet queue to store one or more of the received packets prior to transmitting the packets to the plurality of egress ports,
• a quality of service (QoS) descriptor module to generate a QoS descriptor for each of the received plurality of packets, each of the QoS descriptors to indicate a plurality of QoS characteristics, wherein the QoS descriptor module is to include in the plurality of QoS characteristics for each QoS descriptor an indication of an isolation group (IG) and a class of service (CoS) associated with each of the received plurality of packets,
• a traffic manager module to shape packet traffic and to mark one or more of the plurality of received packets for on-chip packet storage or off-chip packet storage based, at least in part, on that packet's QoS descriptor, wherein at least one of the packets is to be marked for on-chip packet storage and at least one of the packets is to be marked for off-chip packet storage, the traffic manager module is further to,
• verify that the on-chip packet store has available resources dedicated to the CoS of the IG,
• verify that the on-chip packet store has available resources dedicated to the IG,
• verify that the on-chip packet store has globally available resources, and
• mark the packet for off-chip storage or on-chip storage based on the outcome of the on-chip verification steps, and
• wherein, the packet processing core is further to move only those packets that are marked for off-chip packet storage to the off-chip packet store while keeping the other packets in the on-chip packet store until they are transmitted to the egress port;
• whereby at least one of the packet processing cores is to conserve off-chip memory bandwidth by only transferring packets classified for off-chip packet storage to the off-chip packet store.

A method performed in a packet processing core for avoiding memory bandwidth utilization during packet processing, wherein the packet processing core is coupled between a plurality of ingress ports and a plurality of egress ports, the method comprising the steps of:

• receiving a first packet from the plurality of ingress ports;
• building a first quality of service (QoS) descriptor for the first packet, the QoS descriptor comprising a plurality of QoS characteristics;
• storing the first packet in a first packet queue in an on-chip packet store, the first packet queue associated with packets that share one of the first's packets QoS characteristics;
• receiving a second packet from the plurality of ingress ports;
• building a second QoS descriptor for the second packet, wherein the second QoS descriptor includes information identifying an isolation group (IG) and a class of service (CoS) within that IG;
• classifying the second packet for storage in an off-chip packet store based, at least in part, on the second QoS descriptor, wherein the step of classifying the second packet for storage in the off-chip packet store includes,
• determining that the on-chip packet store does not have available resources designated for the IG, and
• determining that the on-chip packet store does not have available resources designated for the CoS within the IG;
• storing the second packet in a second packet queue in an off-chip packet store, the second packet queue associated with packets that share one of the first's packets QoS characteristics;
• and
• whereby off-chip memory bandwidth is conserved because the first packet is classified for on-chip packet storage and is not sent to the second packet queue that is in the off-chip packet store.