MAC processor architecture

A media access control (MAC) processor, comprising:

• a programmable controller configured to execute machine readable instructions for implementing MAC functions corresponding to data received by a communication device;
• tightly coupled memory associated with the programmable controller;
• a system memory coupled to the programmable controller via a system bus, wherein
• the programmable controller accesses data stored in the tightly coupled memory at a first data rate and accesses data stored in the system memory at a second data rate, and
• the first data rate is faster than the second data rate;
• a hardware processor coupled to the system bus and to the tightly coupled memory that is associated with the programmable controller,
• wherein the hardware processor is configured to:
• implement MAC functions on data received in a communication frame,
• store, in the tightly coupled memory, a first subset of data in a first sub-frame of the communication frame that indicates a structure of downlink data in the communication frame, and
• store, in the system memory, a second subset of data in the first sub-frame other than the first subset of data.