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US 8,897,086 B2Granted
Method and apparatus for memory fault tolerance
OwnerCurtis Ling, Vadim Smolyakov +2inventors
InventorsCurtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
Life of this patent
Estimating the term…
Abstract
One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.
Claims14
A system comprising:
- one or more circuits comprising an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module, said one or more circuits being operable to:
- receive a data block to be written to said array of memory cells;
- detect whether said data block contains a first type of data or a second type of data;
- and
- write said data block to said array of memory cells, wherein:
- said data block bypasses said memory fault mitigation module if said data block contains said first type of data;
- and
- said write comprises a swap, in said memory fault mitigation module, of a first portion of said data block with a second portion of said data block if said data block contains said second type of data.
5 more elements
A system comprising:
- one or more circuits comprising an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module, said one or more circuits being operable to:
- determine whether bits of data to be read from said array of memory cells comprise a first type of data or a second type of data;
- and
- read said bits of data from said array of memory cells, wherein said read comprises:
- retrieval of said bits of data from said array of memory cells;
- if said retrieved bits of data comprise said first type of data, a bypass of said memory fault mitigation module;
- and
- if said retrieved bits of data comprise said second type of data, a swap, in said memory fault mitigation module, of a first portion of said retrieved bits of data with a second portion of said retrieved bits of data.
5 more elements
Dependencies are inferred from the claim text.