Memory interface circuitry with data strobe signal sharing capabilities

Abstract

An integrated circuit may include memory interface circuitry for communicating with off-chip memory. The memory interface circuitry may receive data signals and data strobe signals from different memory devices via respective data ports and data strobe ports. The memory interface circuitry may be operable in at least first and second modes. In the first mode, data signals from each memory device may be received at two respective data ports while the data strobe signal from one memory device is used to clock the data signals at two corresponding read capture registers. In the second mode, data signals from first and second memory devices may be received via first and second data ports, respectively. The data strobe signal from the first memory device may be ignored while the data strobe signal from the second memory device is used to clock the data signals at two corresponding read capture registers.

Dependencies are inferred from the claim text.