Variable rate serial to parallel shift register
AssigneeSanDisk Technologies LLC
InventorWanfang Tsai
Life of this patent
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Abstract
A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.
Claims4
A method of transferring data from an m-bit wide serial format to an N by m-bit wide parallel format, where N is an integer two or greater and m is an integer one or greater, comprising:
- receiving a stream of data on a serial bus in an m-bit wide serial format;
- receiving a first clock signal
- accessing information on m-bit units of data to be ignored when being transferred on a parallel bus;
- generating a second clock signal of variable rate based on the first clock signal and upon the information on the units of data that are to be ignored;
- generating one or more first control signals based on the first clock signal and upon the data on units of data that are to be ignored;
- loading data from the serial data bus into one or more m-bit wide data sections of an N section wide latch according to the first clock signal based on the first control signals, wherein redundant entries are entered for units of data to be ignored;
- and
- transferring out N m-bit wide units of data from the latch to the parallel bus according to the second clock signal.
Dependencies are inferred from the claim text.