Semiconductor memory device and method of programming the same
AssigneeSK hynix Inc.
InventorJea Won Choi
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device and a method of programming the same are provided which can improve the program accuracy by classifying cells depending on a program status of memory cells during a program operation to control a bit line program voltage. The method comprises classifying memory cells to be programmed based on program characteristics of the memory cells and sequentially providing word line program voltages having increasing voltage levels and bit line program voltages having decreasing voltage levels to the classified memory cells in a program operation, wherein differently classified two memory cells receive different bit line program voltages, respectively.
Claims19
A method of programming a semiconductor memory device, the method comprising:
- classifying memory cells to be programmed based on program characteristics of the memory cells, wherein the memory cells are coupled to a selected word line;
- and
- sequentially providing word line program voltages having increasing voltage levels and bit line program voltages having decreasing voltage levels to the classified memory cells in one program loop, wherein differently classified memory cells receive different bit line program voltages, respectively.
A semiconductor memory device, comprising:
- a memory cell array including memory cells to be programmed, which are coupled to a selected word line;
- a program control unit configured to classify statuses of the memory cells and generate a row voltage control signal and a column voltage control signal;
- a voltage generator configured to generate word line program voltages and bit line program voltages;
- a row decoder configured to provide the word line program voltages whose voltage levels sequentially increase in one program loop to the selected word line in response to the row voltage control signal;
- and
- a column decoder configured to provide the bit line program voltages whose voltage levels are different depending on the statuses of the memory cells to bit lines coupled to the memory cells in response to the column voltage control signal, the bit line program voltages sequentially decreasing based on the statuses of the memory cells in the one program loop.
A method of programming a semiconductor memory device, the method comprising:
- providing a memory cell in a memory cell array, the memory cell being coupled to a word line and a bit line;
- applying a set of word line program voltages to the word line to program the memory cell;
- and
- applying a set of bit line voltages to the bit line to program the memory cell while the set of word line program voltages is being applied to the word line,
- wherein the applied set of bit line voltages is selected from at least first, second, and third sets based on a program characteristic of the memory cell,
- wherein the first set of bit line voltages includes first, second, and third voltages that are different from each other, the second set of bit line voltages includes only the first voltage and the second voltage, and the third set of the bit line voltages includes only the second voltage, and
- wherein the first voltage has the highest potential of the three, the second voltage has an intermediate potential of the three, and the third voltage has the lowest potential of the three.
Dependencies are inferred from the claim text.