Nonvolatile memory cells and methods of making such cells
AssigneeCypress Semiconductor Corporation
InventorsVenkatraman Prabhakar, Kaveh Shakeri, Long T Hinh, Sarath C. Puthenthermadam
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Abstract
A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.
Claims7
A memory cell, comprising:
- at least a first programmable section coupled between a first supply node and a first data node;
- a volatile storage circuit coupled to the first data node;
- and
- the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first access transistor, and a second S/D region shared with a second access transistor, wherein the first S/D region has a different dopant diffusion profile than the second S/D region and a more graded dopant p-n junction than the second S/D region, wherein a grade increasing region of the same conductivity type as the first S/D region contains the first S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel.
Dependencies are inferred from the claim text.