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US 8,897,059 B2Granted
Resistance change memory device that stores a reversible resistance value as data
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
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Abstract
A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively.
Claims16
A resistance change memory device comprising:
- a memory cell array having a plurality of memory cells each including a variable resistance element, the state of the variable resistance element being reversibly changed between a low resistance state and a high resistance state in accordance with applied voltage or current;
- and
- a voltage control transistor so coupled in series to the memory cell as to prevent the memory cell from being applied with set-use voltage when the memory cell held in a set state with the low resistance state is applied with reset-use current to be changed to a reset state with the high resistance state, wherein
- the set-use voltage is higher than a voltage subtracting a voltage drop of electric elements between a gate of the voltage control transistor and the memory cell from a gate voltage of the voltage control transistor.
1 more element
A resistance change memory device comprising:
- a memory cell array having a plurality of memory cells each including a variable resistance element, the state of the variable resistance element being reversibly changed between a low resistance state and a high resistance state in accordance with applied voltage or current;
- and
- a current control transistor so coupled in series to the memory cell as to prevent the memory cell from being applied with reset-use current when the memory cell held in the reset state with the high resistance state is applied with set-use voltage to be changed to the set state with the low resistance state, wherein
- the current control transistor operates under such a gate bias condition that the current is clamped under a certain saturation current level when the memory cell held in the reset state with the high resistance state is applied with the set-use voltage to be changed to the set state with the low resistance state, and
- the reset-use current is higher than the certain saturation current level.
2 more elements
A resistance change memory device comprising:
- a memory cell array having a plurality of first lines, a plurality of second lines crossing to the plurality of first lines, and a plurality of memory cells disposed at a crossing point of the first line and the second line, each memory cell including a variable resistance element, the state of the variable resistance element being reversibly changed between a low resistance state and a high resistance state in accordance with applied voltage or current;
- a first line select circuit which connects to the plurality of first lines to select a part of the first lines, and
- a current control transistor so coupled in series to the memory cell as to prevent the memory cell from being applied with reset-use current when the memory cell held in the reset state with the high resistance state is applied with set-use voltage to be changed to the set state with the low resistance state, wherein
- the current control transistor operates under such a gate bias condition that the current is clamped under a certain saturation current level when the memory cell held in the reset state with the high resistance state is applied with set-use voltage to be changed to the set state with the low resistance state, and
- the reset-use current is higher than the certain saturation current level.
2 more elements
Dependencies are inferred from the claim text.