Memory device, method of operating the same, and electronic device having the memory device

A memory device comprising:

• a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines;
• a memory control circuit configured to select one or more memory cells in the memory cell array;
• a first fuse cell array including a plurality of fuse cells coupled to a first plurality of fuse word lines and a first plurality of fuse bit lines, the first fuse cell array configured to store first data;
• a second fuse cell array including a plurality of fuse cells coupled to a second plurality of fuse word lines and a second plurality of fuse bit lines, the second fuse cell array configured to store second data;
• and
• a fuse control circuit configured to read the first and second data from the first and second fuse cell arrays, respectively, and to transfer the data to the memory control circuit,
• wherein the first data is associated with operation of the fuse control circuit, and the second data is associated with operation of the memory device, and
• wherein the first and second plurality of fuse word lines are the same word lines, or wherein the first and second plurality of fuse bit lines are the same bit lines.