Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

A method of aligning signal timing in a semiconductor memory device, the method comprising:

• a) identifying a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices, wherein the plurality of semiconductor devices are coupled together via a common vertical connection of a data strobe;
• b) detecting a phase of the data strobe relative to an internal data signal;
• and
• c) delaying the internal data signal to substantially match the data strobe, wherein the data strobe is driven by one of the plurality of semiconductor memory devices based on the stack position identifier.

An apparatus having an aligned vertical stack of a plurality of semiconductor memory devices, the apparatus comprising for a semiconductor memory device:

• a) a stack position identifier for identifying a position of the semiconductor memory device in the aligned vertical stack of the plurality of semiconductor memory devices, wherein the plurality of semiconductor devices are coupled together via a common vertical connection of a data strobe;
• b) a phase detector configured to detect a phase of the data strobe relative to an internal data signal;
• and
• c) a phase adjustor configured to delay the internal data signal to substantially match the data strobe, wherein the data strobe is driven by one of the plurality of semiconductor memory devices based on the stack position identifier.