Semiconductor device and memory device including semiconductor device
AssigneeSemiconductor Energy Laboratories Co., Ltd.
InventorKazuma Furutani
Life of this patent
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Abstract
To provide a semiconductor device whose power can be turned off without the need for a peripheral circuit for data to escape temporarily and in which stored data is not lost even in an off state of the power of the device, and a memory device including the semiconductor device. In a holding circuit of the semiconductor device, a transistor that includes a semiconductor layer (at least a channel formation region) including an oxide semiconductor material with which small off-state current can be achieved is used. Further, the semiconductor device includes a switching element which enables a comparison circuit in which comparison between data stored in the holding circuit and reference data input from the outside does not need to be performed to become forcibly inactive.
Claims21
A semiconductor device comprising:
- a holding circuit comprising a first transistor and a capacitor electrically connected to the first transistor;
- a comparison circuit comprising:
- a first arithmetic circuit comprising a second transistor and a third transistor electrically connected to the second transistor;
- and
- a second arithmetic circuit comprising a fourth transistor and a fifth transistor electrically connected to the fourth transistor;
- and
- a switching element,
- wherein the first transistor includes a first oxide semiconductor layer,
- wherein the holding circuit is electrically connected to the first arithmetic circuit and the second arithmetic circuit,
- wherein the first arithmetic circuit is electrically connected to the second arithmetic circuit,
- wherein the switching element is electrically connected to the first arithmetic circuit and the second arithmetic circuit,
- wherein the first arithmetic circuit and the second arithmetic circuit are configured to change a potential of a output signal line electrically connected to the switching element, and
- wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the capacitor, a gate electrode of the third transistor, and a gate electrode of the fifth transistor.
A semiconductor device comprising:
- a holding circuit comprising a first transistor and a capacitor electrically connected to the first transistor, wherein storage data is input to the capacitor;
- a comparison circuit comprising:
- a first arithmetic circuit comprising a second transistor and a third transistor electrically connected to the second transistor;
- and
- a second arithmetic circuit comprising a fourth transistor and a fifth transistor electrically connected to the fourth transistor;
- and
- a switching element,
- wherein reference data is input to each of the first arithmetic circuit and the second arithmetic circuit so that the first arithmetic circuit and the second arithmetic circuit each compares the storage data with the reference data,
- wherein the first transistor includes a first oxide semiconductor layer,
- wherein the holding circuit is electrically connected to the first arithmetic circuit and the second arithmetic circuit,
- wherein the first arithmetic circuit is electrically connected to the second arithmetic circuit,
- wherein the switching element is electrically connected to the first arithmetic circuit and the second arithmetic circuit, and
- wherein the first arithmetic circuit and the second arithmetic circuit is configured to change a potential of a output signal line electrically connected to the switching element when at least one of the first arithmetic circuit and the second arithmetic circuit and the switching element are in a conductive state, and
- wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the capacitor, a gate electrode of the third transistor, and a gate electrode of the fifth transistor.
Dependencies are inferred from the claim text.