US 8,896,635 B2 · Display device

a plurality of pixels;

a plurality of scanning lines for inputting a scanning voltage to the plurality of pixels, assuming N as an integer of 2 or more, the plurality of scanning lines being divided into scanning groups ranging from first scanning groups to Nth scanning groups by hierarchical grouping, the hierarchical grouping being performed sequentially such that the plurality of scanning lines are divided into a plurality of first scanning groups, the plurality of first scanning groups are divided into a plurality of second scanning groups, a plurality of (N−2)th scanning groups are divided into a plurality of (N−1)th scanning groups, and the plurality of (N−1)th scanning groups are divided into a plurality of N-th scanning groups, each of the first scanning groups including anywhere from 1 to k1 number of the scanning lines, each of the second scanning groups including k2 number of the first scanning groups, each of the Nth scanning groups including kN number of the (N−1)th scanning groups sequentially;

a scanning line drive circuit which supplies the scanning voltage to the plurality of scanning lines;

a group of gate lines sequentially ranging from k1 number of gate lines belonging to a first group and k2 number of gate lines belonging to a second group to kN number of gate lines belonging to an Nth group, the group of gate lines being connected to the scanning line drive circuit;

a group of reverse gate lines sequentially raging from k2 number of reverse gate lines belonging to the second group to kN number of reverse gate lines belonging to the Nth group, the group of reverse gate lines being connected to the scanning line drive circuit;

and

a plurality of control circuits being respectively arranged on the plurality of scanning lines, each of the plurality of control circuits including (2N−2) number of transistors ranging from a first transistor to a (2N−2)th transistor,

each of the (2N−2) number of transistors including a first electrode, a second electrode, and a control electrode,

(N−1) number of transistors ranging from the first transistor to the (N−1)th transistor being connected to each other in series,

the second electrode of the (N−1)th transistor being connected to one of the plurality of scanning lines,

(N−1) number of transistors ranging from the Nth transistor to the (2N−2)th transistor being connected to the one of the plurality of scanning lines via the first electrode thereof parallel to each other,

a predetermined reference potential being respectively applied to the second electrodes of the (N−1) number of transistors ranging from the Nth transistor to the (2N−2)th transistor,

the first electrode of the first transistor being connected to any one of the gate lines belonging to the first group,

the control electrodes of the first to (N−1)th transistors being sequentially connected such that the control electrode of the first transistor is connected to any one of the gate lines belonging to the second group, and the control electrode of the (N−1)th transistor is connected to any one of the gate lines belonging to the Nth group,

the control electrodes of the Nth to (2N−2)th transistors being sequentially connected such that the control electrode of the Nth transistor is connected to any one of reverse gate lines belonging to the second group, and the control electrode of the (2N−2)th transistor is connected to any one of the reverse gate lines belonging to the Nth group, wherein:

the control electrodes of the first transistors in the control circuits connected to the scanning lines belonging to each first scanning group are all connected to same one of the gate lines belonging to the second group;

the control electrodes of the (N−1)th transistors in the control circuits connected to the scanning lines belonging to each (N−1)th group are all connected to same one of the gate lines belonging to the Nth group sequentially;

the control electrodes of the Nth transistors in the control circuits connected to the scanning lines belonging to each first scanning group are all connected to same one of the reverse gate lines belonging to the second group,

the control electrodes of the (2N−2)th transistors in the control circuits connected to the scanning lines belonging to each (N−1)th group are all connected to same one of the reverse gate lines belonging to the Nth group sequentially,

when selective scanning voltages are respectively applied to any one of the gate lines belonging to the second group to any one of the gate lines belonging to the Nth group, and non-selective reversal scanning voltages are respectively applied to any one of the reverse gate lines belonging to the second group to any one of the reverse gate lines belonging to the Nth group, wherein both the any one of the gate lines belonging to the second group to the any one of the gate lines belonging to the Nth group and the any one of the reverse gate lines belonging to the second group to the any one of the reverse gate lines belonging to the Nth group are all connected to the control circuits being connected to the scanning lines belonging to same one of the first scanning groups, so that the first to (N−1)th transistors being connected to the scanning lines belonging to the same one of the first scanning groups are turned on and the Nth to (2N−2)th transistors being connected to the scanning lines belonging to the same one of the first scanning groups are turned off;

and

when a non-selective scanning voltage is applied to at least one gate line ranging from the any one of the gate lines belonging to the second group to the any one of the gate lines belonging to the Nth group, a selective reversal scanning voltage is intermittently applied to at least one gate line ranging from the any one of the reverse gate lines belonging to the second group to the any one of the gate lines belonging to the Nth group, so that at least one of the first to (N−1)th transistors in the control circuits being connected to the same one of the first scanning groups is turned off and at least one of the Nth to (2N−2)th transistors in the control circuits being connected to the same one of the first scanning groups is intermittently turned on.

Display device

Life of this patent

Display device

Life of this patent

Abstract

Claims11