Error recovery operations for a hardware accelerator
AssigneeTexas Instruments Incorporated
InventorsResmi Rajendran, Pavan Venkata Shastry
Life of this patent
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Abstract
In at least some embodiments, an apparatus includes a hardware accelerator subsystem with a pipeline. The hardware accelerator subsystem is configured to perform error recovery operations in response to a bit stream error. The error recovery operations comprise a pipe-down process to completely decode a data block that is already in the pipeline, an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete, and a pipe-up process to restart decoding operations of the pipeline at a next synchronization point.
Claims17
An apparatus comprising:
- a hardware accelerator subsystem with a pipeline, wherein the hardware accelerator subsystem is configured to perform error recovery operations in response to a bit stream error,
- wherein the error recovery operations comprise a pipe-down process to completely decode a data block that is already in the pipeline, an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete, and a pipe-up process to restart decoding operations of the pipeline at a next synchronization point, and wherein, during the overwrite process, ping state commands of the hardware accelerator subsystem are directly overwritten with NOPs by a sequencer component.
An apparatus comprising:
- a hardware accelerator subsystem with a pipeline, wherein the hardware accelerator subsystem is configured to perform error recovery operations in response to a bit stream error, wherein the error recovery operations comprise a pipe-down process to completely decode a data block that is already in the pipeline, an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete, and a pipe-up process to restart decoding operations of the pipeline at a next synchronization point, and wherein, during the overwrite process, pong state commands of the hardware accelerator subsystem are overwritten by a load/store engine that loads the NOPs to an auxiliary buffer of the hardware accelerator subsystem.
A semiconductor chip comprising:
- a hardware accelerator having a video encoder/decoder component with a pipeline and with error recovery logic, wherein the error recovery logic is configured to:
- perform pipe-down operations to clear the pipeline without interrupting ongoing tasks;
- stall end of task signaling;
- wait for a predetermined number of data blocks to come out of the pipeline and for a predetermined number of load activations for the video encoder/decoder component;
- load null operations (NOPs) to the video encoder/decoder component;
- release the end of task signaling;
- and
- perform pipe-up operations to restart the pipeline at a next synchronization point, wherein the pipe-up operations cause the error recovery logic of the video encoder/decoder component to:
- update load/store engine counters of the video encoder/decoder component;
- update video direct memory access (vDMA) descriptors;
- and
- correct an address mapped register of a first sequencer and a second sequencer of the video encoder/decoder component.
A method for error recovery in a hardware accelerator subsystem with a video decoding pipeline, the method comprising:
- performing a pipe-down process to completely decode a data block that is already in the video decoding pipeline;
- performing an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete including directly overwriting ping state commands of the hardware accelerator subsystem with NOPs by a sequencer component;
- and
- performing a pipe-up process to restart operations of the video decoding pipeline after a predetermined store operation associated with a final stage of the pipeline is complete.
A method for error recovery in a hardware accelerator subsystem with a video decoding pipeline, the method comprising:
- performing a pipe-down process to completely decode a data block that is already in the video decoding pipeline;
- performing an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete including overwriting pong state commands of the hardware accelerator subsystem by loading the NOPs to an auxiliary buffer of the hardware accelerator subsystem;
- and
- performing a pipe-up process to restart operations of the video decoding pipeline after a predetermined store operation associated with a final stage of the pipeline is complete.
Dependencies are inferred from the claim text.