Gate driving method for controlling display apparatus and gate driver using the same

A gate driver for controlling a display apparatus, the gate driver comprising:

• a logic circuit generating a plurality of switch signals;
• a plurality of buffers coupled to the logic circuit, each of the buffers comprising a first end coupled to the logic circuit, a second end coupled to a first voltage source, a third end coupled to a second voltage source, and an output end coupled to a load module, wherein each of the buffers determines to provide a first voltage or a second voltage according to one of the switch signals to generate a gate driving signal;
• and
• a charge sharing module coupled to the output ends of the buffers and allowing the output ends of the buffers to share charges according to a plurality of sharing signals during a forward edge and a backward edge of a square wave of each of the gate driving signals, wherein the charge sharing module comprises:
• a plurality of third switches coupled between the output ends of the corresponding buffers, the third switches sequentially electrically connecting corresponding buffers of the buffers according to a first sharing signal during the forward edges and the backward edges of the square waves of the gate driving signals;
• and
• a plurality of fourth switches coupled between the output ends of the corresponding buffers, the fourth switches sequentially electrically connecting corresponding buffers of the buffers according to a second sharing signal during the forward edges and the backward edges of the square waves of the gate driving signals, wherein when the third switches electrically connect the buffers corresponding to the third switches according to the first sharing signal, the fourth switches electrically isolate the buffers corresponding to the fourth switches from one another according to the second sharing signal, and when the fourth switches electrically connect the buffers corresponding to the fourth switches according to the second sharing signal, the third switches electrically isolate the buffers corresponding to the third switches from one another according to the first sharing signal.