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US 8,896,513 B2Granted
Gamma bus amplifier offset cancellation
AssigneeApple Inc.
InventorYafei Bi
Life of this patent
Estimating the term…
Abstract
The present disclosure generally relates to gamma bus wiring techniques that saves space in a display such as a liquid crystal display. In certain embodiments, a voltage offset associated with gamma bus amplifiers configured to provide analog voltage levels to a pixel may reduce at least some of the visual performance characteristics of the attached display when it transitions between different voltage values provided by different gamma bus amplifiers. The voltage offsets associated with the gamma bus amplifiers may be distributed between multiplexers that are coupled to gamma bus amplifiers by interlacing the wires routed from a resistor string to the multiplexers.
Claims23
A gamma adjustment circuitry, comprising:
- a resistor string configured to provide 2N voltage levels on 2N respective nodes that correspond to 2N respective gray levels to be displayed in an N-bit unit pixel of a display panel;
- a set of multiplexers, wherein each multiplexer in the set of multiplexers is coupled to a respective subset of the 2N respective nodes, wherein a plurality of adjacent nodes that correspond to a respective plurality of adjacent gray levels in two respective subsets of the 2N respective nodes is interlaced between two respective multiplexers in the set of multiplexers;
- a set of amplifiers, wherein each amplifier in the set of amplifiers is coupled to a respective multiplexer in the set of multiplexers;
- and
- a source driver coupled to the set of amplifiers, wherein the source driver supplies a voltage that corresponds to one of the 2N voltage levels to the N-bit unit pixel.
2 more elements
A display device, comprising
- a display panel comprising a plurality of N-bit pixels defining a viewable region of the display device;
- and
- a source driver integrated circuit (IC) configured to process an image data stream and to transmit the processed image data to the display panel, wherein the source driver IC comprises:
- a gamma adjustment circuitry, comprising:
- a resistor string configured to provide 2N voltage levels on 2N respective nodes that correspond to 2N respective gray levels to be displayed in one of the plurality of N-bit unit pixels;
- a set of multiplexers, wherein each multiplexer in the set of multiplexers is coupled to a respective subset of the 2N respective nodes, wherein a plurality of adjacent nodes that correspond to a respective plurality of adjacent gray levels in at least two respective subsets of the 2N respective nodes is interlaced between at least two respective multiplexers in the set of multiplexers, wherein a number of the at least two respective subsets of the 2N respective nodes is the same as a number of the at least two respective multiplexers;
- a set of amplifiers, wherein each amplifier in the set of amplifiers is coupled to a respective multiplexer in the set of multiplexers;
- and
- a source driver coupled to the set of amplifiers, wherein the source driver supplies a voltage that corresponds to one of the 2N voltage levels to the one of the plurality of N-bit pixels.
6 more elements
An electronic device, comprising:
- one or more input devices;
- a memory capable of storing executable instructions;
- a processor configured to receive inputs from the one or more input devices and to execute the executable instructions;
- and
- a liquid crystal display (LCD) having a source driver integrated circuit (IC) configured to process an image data stream and to transmit the processed image data to the LCD, wherein the source driver IC comprises:
- a gamma adjustment circuitry, comprising:
- a resistor string configured to provide 2N voltage levels on 2N respective nodes that correspond to 2N respective gray levels to be displayed on an N-bit unit pixel in the LCD;
- a set of multiplexers, wherein each multiplexer in the set of multiplexers is coupled to a respective subset of the 2N respective nodes, wherein a plurality of adjacent nodes that correspond to a respective plurality of adjacent gray levels in at least two respective subsets of the 2N respective nodes is interlaced between at least two respective multiplexers in the set of multiplexers, wherein a number of the at least two respective subsets of the 2N respective nodes is the same as a number of the at least two respective multiplexers;
- a set of amplifiers, wherein each amplifier in the set of amplifiers is coupled to a respective multiplexer in the set of multiplexers;
- and
- a source driver coupled to the set of amplifiers, wherein the source driver supplies a voltage that corresponds to one of the 2N voltage levels to the N-bit unit pixel in the LCD.
8 more elements
A method, comprising:
- receiving image data comprising 2N gray levels to be displayed in an N-bit unit pixel of a display panel, wherein the 2N gray levels correspond to 2N respective voltage levels;
- multiplexing a plurality of respective subsets of the 2N respective voltage levels using a plurality of respective multiplexers, thereby generating a plurality of respective multiplexed signals, wherein each of at least two respective multiplexers in the plurality of respective multiplexers multiplexes a plurality of adjacent voltage levels that correspond to a plurality of adjacent gray levels from each of at least two respective subsets of the 2N respective voltage levels, wherein a number of the at least two respective multiplexers is the same as a number of the at least two respective subsets of the 2N respective nodes;
- buffering each of the plurality of respective multiplexed signals, thereby generating a plurality of respective buffered multiplexed signals;
- decoding one of the plurality of respective buffered multiplexed signals one voltage level of the 2N respective voltage levels;
- and
- sending the one voltage level to the N-bit unit pixel.
3 more elements
Dependencies are inferred from the claim text.