Successive approximation analog-to-digital converter using capacitor array with sub-capacitors configured by capacitor disassembling and related method thereof
AssigneeRealtek Semiconductor Corp.
InventorsJen-Huan Tsai, Po-Chiun Huang
Life of this patent
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Abstract
A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N−1) unit capacitors, M>N, and M and N are both positive integers. The comparator is arranged for comparing an output of the capacitor array and an analog input sequentially.
Claims8
A successive approximation analog-to-digital converter (SAR ADC), comprising:
- a capacitor array, comprising M capacitors arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N−1) unit capacitors, M>N, and M and N are both positive integers;
- and a sum of capacitance values of a plurality of specific capacitors among the M capacitors is equal to 2k unit capacitors, where K is a positive integer and K<N;
- and
- a comparator, arranged for comparing an output of the capacitor array and an analog input sequentially.
A successive approximation analog-to-digital conversion method, comprising:
- controlling a capacitor array to make M capacitors perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N−1) unit capacitors, M>N, and M and N are both positive integers;
- and a sum of capacitance values of a plurality of specific capacitors among the M capacitors is equal to 2k unit capacitors, where K is a positive integer and K<N;
- and
- comparing an output of the capacitor array with an analog input sequentially.
Dependencies are inferred from the claim text.