Data-driven noise reduction technique for analog to digital converters
AssigneeTechnische Universiteit Eindhoven
InventorPieter Joost Adriaan Harpe
Life of this patent
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Abstract
A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τMV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τMV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.
Claims6
A successive operation register (SAR) analog-to-digital converter (ADC) circuit comprising:
- a voltage comparator having a first analog signal input, a second analog input, and a decision output;
- a decision logic circuit having an input connected to the decision output of the voltage comparator and a digital output;
- a digital-to-analog converter (DAC) having a digital input connected to the digital output of the decision logic circuit and an analog output connected to the second analog input of the voltage comparator;
- further comprising:
- a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τMV, outputs a bit reliability decision signal;
- a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τMV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator.
Dependencies are inferred from the claim text.