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US 8,896,475 B2Granted
Continuous-time oversampling pipeline analog-to-digital converter
AssigneeAnalog Devices Technology
InventorHajime Shibata
Life of this patent
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Abstract
A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.
Claims27
A converter, comprising:
- a plurality of converter stages connected in series, each receiving a clock signal and a respective continuous-time analog input voltage, and generating a respective analog output signal and a respective digital output signal;
- wherein intermediate converter stages each comprise:
- an encoder generating, based on the respective continuous-time analog input voltage and the clock signal, the respective digital output signal;
- a decoder generating, based on the respective digital output signal and the clock signal, a respective reconstructed signal as a current signal;
- a delaying converter generating, based on the respective continuous-time analog input voltage, a respective delayed signal as a continuous-time current signal;
- and
- an amplifier generating, based on a comparison of the currents representing the respective delayed signal and the respective reconstructed signal, a respective residue signal.
4 more elements
A method, comprising:
- generating by an encoder, based on a continuous-time analog input voltage and a clock signal, a digital output signal;
- generating by a decoder, based on the digital output signal and the clock signal, a reconstructed signal as a current signal;
- generating by a delaying converter, based on the continuous-time analog input voltage, a delayed signal as a continuous-time current signal;
- generating by an amplifier, based on a comparison of the currents representing the delayed signal and the reconstructed signal, a residue signal.
1 more element
A converter, comprising:
- a plurality of pipelined converter stages, each having an output for a digital signal, an input for an input voltage and an input for a clock signal, wherein:
- a first stage receives an input voltage signal to be converted and generates an residual voltage signal to a next converter stage,
- each intermediate converter stage receives the residual voltage signal from a respective preceding stage and outputs its residual voltage signal to a next converter stage,
- wherein the intermediate converter stages each comprise:
- a clocked encoder to generate the stage's respective digital output signal;
- a clocked decoder to generate from a current signal representing the stage's respective digital output signal;
- an unclocked delay unit to generate from, the stage's respective input voltage, a continuous-time current signal representing a delayed version of the stage's input voltage;
- and
- an amplifier to generate from a comparison of the currents from the decoder and the delay unit, the stage's residue signal.
6 more elements
Dependencies are inferred from the claim text.