Low glitch-noise DAC

A digital-to-analog converter (DAC) comprising:

• a first plurality of parallel stages associated with most significant bits of the DAC, each of the first plurality of stages adapted to generate a current and deliver the current to a pair of current summing nodes of the DAC via a pair of switches responsive to differential data;
• a second plurality of stages associated with least significant bits of the DAC, each of the second plurality of stages generating the current and comprising a resistive network, each of the second plurality of stages further comprising a pair of switches adapted to deliver the current generated in the stage to the stage's associated resistive network in response to differential data, each resistive network operable to scale the current it receives and deliver a scaled current defined by a binary weight of its associated stage, the second plurality of stages delivering their scaled currents to the pair of current summing nodes;
• and
• an impedance attenuator comprising a differential amplifier coupled to the pair of summing nodes and adapted to maintain an impedance of each of the current summing nodes and a voltage difference between the current summing nodes within a range defined by a gain of the differential amplifier.

A method of converting an N-bit digital signal to an analog signal, the method comprising:

• forming 2M−1 parallel stages associated with M most significant bits of the digital data;
• generating a current in each of the 2M−1 stages;
• delivering the current generated in each of the 2M−1 stages to a pair of current summing nodes via a first pair of switches responsive to differential data;
• forming (N−M) stages associated with (N−M) least significant bits of the digital data;
• generating the current in each of the (N−M) stages;
• forming (N−M) resistive networks each associated with a different one of the (N−M) stages;
• delivering to each of the (N−M) resistive networks the current generated in its associated stage via a second pair of switches responsive to differential data;
• scaling the current received by each resistive network in accordance with a binary weight of the resistive network's associated stage,
• delivering the scaled currents to the pair of current summing nodes;
• maintaining an impedance of each of the current summing nodes within a range defined by a gain value;
• and
• maintaining a voltage difference between the current summing nodes within a range defined by the gain value, the difference in the currents delivered to the current summing nodes defining a value of the analog signal.

A method of converting a digital signal to an analog signal, the method comprising:

• forming a first plurality of parallel stages associated with most significant bits of the digital data;
• generating a current in each of the first plurality of parallel stages;
• delivering the current generated in each of the first plurality of parallel stages to a pair of current summing nodes via a first pair of switches responsive to differential data;
• forming a second plurality of stages associated with least significant bits of the digital data;
• generating the current in each of the second plurality of stages;
• forming a first plurality of resistive networks each associated with a different one of the second plurality of stages;
• delivering to each of the first plurality of resistive networks the current generated in its associated stage via a second pair of switches responsive to differential data;
• scaling the current received by each of the first plurality of resistive network in accordance with a binary weight of the resistive network's associated stage,
• delivering the scaled currents to the pair of current summing nodes;
• maintaining an impedance of each of the current summing nodes within a range defined by a gain value;
• and
• maintaining a voltage difference between the current summing nodes within a range defined by the gain value, the difference in the currents delivered to the current summing nodes defining a value of the analog signal.

An N-bit digital-to-analog converter (DAC) comprising:

• means for forming 2M−1 parallel stages associated with M most significant bits of digital data;
• means for generating a current in each of the 2M−1 stages;
• means for delivering the current generated in each of the 2M−1 stages to a pair of current summing nodes;
• means for forming (N−M) stages associated with (N−M) least significant bits of the digital data;
• means for generating the current in each of the (N−M) stages;
• means for forming (N−M) resistive networks each associated with a different one of the (N−M) stages;
• means for delivering to each of the (N−M) resistive networks the current generated in its associated stage;
• means for scaling the current received by each resistive network in accordance with a binary weight of the resistive network's associated stage,
• means for delivering the scaled currents to the pair of current summing nodes;
• means for maintaining an impedance of each of the current summing nodes within a range defined by a gain value;
• and
• means for maintaining a voltage difference between the current summing nodes within a range defined by the gain value, the difference in the currents delivered to the current summing nodes defining a value of the analog signal.

A digital-to-analog converter comprising:

• means for forming a first plurality of parallel stages associated with most significant bits of the digital data;
• means for generating a current in each of the first plurality of parallel stages;
• means for delivering the current generated in each of the first plurality of parallel stages to a pair of current summing nodes;
• means for forming a second plurality of stages associated with (N−M) least significant bits of the digital data;
• means for generating the current in each of the second plurality stages;
• means for forming a first plurality of resistive networks each associated with a different one of the second plurality of stages;
• means for delivering to each of the first plurality of resistive networks the current generated in its associated stage;
• means for scaling the current received by each resistive network in accordance with a binary weight of the resistive network's associated stage,
• means for delivering the scaled currents to the pair of current summing nodes;
• means for maintaining an impedance of each of the current summing nodes within a range defined by a gain value;
• and
• means for maintaining a voltage difference between the current summing nodes within a range defined by the gain value, the difference in the currents delivered to the current summing nodes defining a value of the analog signal.