Charge pump system

A charge pump system, comprising:

• a clock generator for generating a clock group comprising a first clock, a second clock, a third clock and a fourth clock;
• a boosting unit determination device for generating a number control signal;
• a charge pump circuit for receiving an operating voltage, the number control signal and the clock group, and generating an output voltage, wherein the charge pump circuit comprises plural boosting units, wherein a first portion of the plural boosting units are controlled by the clock group according to the number control signal, and the operating voltage is converted into the output voltage by the first portion of the plural boosting units;
• and
• a voltage regulator for receiving the output voltage and converting the output voltage into a specified regulated voltage;
• wherein a first boosting unit of the plural boosting units comprises:
• a first capacitor;
• a second capacitor;
• a first P-type transistor, wherein the second clock is transmitted to a gate terminal of the first P-type transistor through the first capacitor, the third clock is transmitted to a drain terminal of the first P-type transistor through the second capacitor, and a source terminal of the first P-type transistor is connected with an input terminal of the first boosting unit;
• a second P-type transistor, wherein a gate terminal of the second P-type transistor is connected with the input terminal of the first boosting unit, a source terminal of the second P-type transistor is connected with the gate terminal of the first P-type transistor, and a drain terminal of the second P-type transistor is connected with the drain terminal of the first P-type transistor;
• and a third P-type transistor, wherein a source terminal of the third P-type transistor is connected with the drain terminal of the second P-type transistor, and a drain terminal of the third P-type transistor is connected with an output terminal of the first boosting unit;
• wherein a second boosting unit of the plural boosting units comprises:
• a third capacitor;
• a fourth capacitor;
• a fourth P-type transistor, wherein the fourth clock is transmitted to a gate terminal of the fourth P-type transistor through the third capacitor, the first clock is transmitted to a drain terminal of the fourth P-type transistor through the fourth capacitor, and a source terminal of the fourth P-type transistor is connected with the output terminal of the first boosting unit;
• a fifth P-type transistor, wherein a gate terminal of the fifth P-type transistor is connected with the output terminal of the first boosting unit, a source terminal of the fifth P-type transistor is connected with the gate terminal of the fourth P-type transistor, and a drain terminal of the fifth P-type transistor is connected with the drain terminal of the fourth P-type transistor;
• and a sixth P-type transistor, wherein a source terminal of the sixth P-type transistor is connected with the drain terminal of the fifth P-type transistor, and a drain terminal of the sixth P-type transistor is connected with an output terminal of the second boosting unit;
• and
• wherein a gate terminal of the third P-type transistor is connected with the gate terminal of the fourth P-type transistor.