Control circuit for controlling a push-pull circuit and method thereof

A control circuit for generating a first control signal and a second control signal, comprising:

• an inverter, arranged for inverting an input clock to generate an inverted clock;
• a first delay circuit, arranged for delaying the first control signal to generate a first delay control signal;
• a second delay circuit, arranged for delaying the second control signal to generate a second delay control signal;
• a first mask circuit, coupled to the first delay circuit and the input clock, arranged for filtering out the first delay control signal not larger than a first time period to generate a first mask signal according to the input clock, wherein the first mask circuit comprises:
• a delay circuit, arranged for delaying the first time period of the input clock to generate a delayed clock;
• a first clock edge generator, arranged for generating a first clock edge signal according to specific clock edges of the input clock;
• a second clock edge generator, arranged for generating a second clock edge signal according to specific clock edges of the delayed clock;
• a latch, having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is arranged for receiving the first clock edge signal, the second input terminal is arranged for receiving the second clock edge signal, and the output terminal is arranged for outputting a latch output signal;
• and
• a logic circuit, arranged for generating the first mask signal according to the latch output signal and the first delay control signal;
• a second mask circuit, coupled to the second delay circuit and the inverted input clock, arranged for filtering out the second delay control signal not larger than a second time period to generate a second mask signal according to the inverted input clock;
• a first logic determining circuit, arranged for generating the first control signal to the first delay circuit according to the second mask signal and the input clock;
• and
• a second logic determining circuit, arranged for generating the second control signal to the second delay circuit according to the first mask signal and the inverted input clock.

A control circuit for generating a first control signal and a second control signal, comprising:

• an inverter, arranged for inverting an input clock to generate an inverted clock;
• a first delay circuit, arranged for delaying the first control signal to generate a first delay control signal;
• a second delay circuit, arranged for delaying the second control signal to generate a second delay control signal;
• a first mask circuit, coupled to the first delay circuit and the input clock, arranged for filtering out the first delay control signal not larger than a first time period to generate a first mask signal according to the input clock;
• a second mask circuit, coupled to the second delay circuit and the inverted input clock, arranged for filtering out the second delay control signal not larger than a second time period to generate a second mask signal according to the inverted input clock;
• a first logic determining circuit, arranged for generating the first control signal to the first delay circuit according to the second mask signal and the input clock, wherein the first logic determining circuit comprises:
• a latch, having a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal is arranged for receiving the input clock, the second input terminal is arranged for receiving the second mask signal, and the output terminal is arranged for outputting the first control signal;
• and
• a second logic determining circuit, arranged for generating the second control signal to the second delay circuit according to the first mask signal and the inverted input clock.

A control method for generating a first control signal and a second control signal, comprising:

• inverting an input clock to generate an inverted clock;
• delaying the first control signal to generate a first delay control signal;
• delaying the second control signal to generate a second delay control signal;
• filtering out the first delay control signal not larger than a first time period to generate a first mask signal according to the input clock;
• filtering out the second delay control signal not larger than a second time period to generate a second mask signal according to the inverted input clock;
• generating the first control signal according to the second mask signal and the input clock;
• generating the second control signal according to the first mask signal and the inverted input clock;
• transmitting the first control signal to a gate of a P-type transistor;
• and
• transmitting the second control signal to a gate of an N-type transistor;
• wherein the first time period and the second time period are larger than a summation of a largest delay time of the first control signal and the second control signal and a largest delay time of the P-type transistor and the N-type transistor.