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US 8,896,360 B2Granted
Level-up shifter circuit for high speed and low power applications
AssigneeCavium, Inc.
InventorDavid Lin
Life of this patent
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Abstract
A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity.
Claims24
A level-up shifter circuit comprising:
- a first buffer configured to receive an input signal in a first power domain;
- first, second and third transistors connected in series between a source rail in a second power domain and a ground rail, gates of the second and third transistors connected to an output of the first buffer, the second power domain being distinct from the first power domain;
- second and third buffers connected in series, an output of the second buffer being connected to an input of the third buffer, an input of the second buffer being connected to a node between the second and third transistors, the third buffer outputting an output signal in the second power domain;
- fourth and fifth transistors having respective gates connected to the input signal and respective drains connected to a gate of the first transistor, wherein a node between the second and third buffers is connected to the gate of the first transistor via the fourth transistor;
- and
- sixth and seventh transistors connected in series between the ground rail and a node between the second and third buffers.
3 more elements
A level-up shifter circuit comprising:
- a first buffer configured to receive an input signal in a first power domain;
- first, second and third transistors connected in series between a source rail in a second power domain and ground rail, gates of the second and third transistors connected to an output of the first buffer, the second power domain being distinct from the first power domain;
- second and third buffers connected in series, an output of the second buffer being connected to an input of the third buffer, an input of the second buffer being connected to a node between the second and third transistors, the third buffer outputting an output signal in the second power domain;
- fourth and fifth transistors having respective gates connected to the input signal and respective drains connected to a gate of the first transistor, the fourth transistor having a source continuously connected to a node between the second and third buffers;
- and
- sixth and seventh transistors connected in series between the ground rail and a node between the second and third buffers.
3 more elements
Dependencies are inferred from the claim text.