A temperature compensated timing signal generator for generating a succession of temperature compensated time unit signal pulses, said time unit of the signal pulses being an arbitrary predefined time interval, the timing signal generator comprising:
- a crystal oscillator configured to generate a reference time signal, and a divider circuit arranged to receive the reference time signal as input and to output a coarse time unit signal, the reference time signal and the coarse time unit signal each having an actual frequency deviating from a corresponding desired frequency as a function of the temperature of said crystal oscillator;
- a high frequency oscillator configured to generate an interpolation signal having an actual frequency (fRC) greater than an actual frequency (fXT) of the crystal oscillator, wherein the actual frequency of the crystal oscillator is the same as the actual frequency of the reference time signal;
- a temperature signal generation circuit comprising a temperature sensor in thermal contact with the crystal oscillator and configured to provide and refresh periodically a digital temperature signal representative of the temperature of said crystal oscillator;
- a finite state machine configured with calibration data so as to compute for each time unit signal pulse, as a function of the digital temperature signal (M(T)), a deviation compensating signal comprising an integer part (K−1) representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part (n) representative of how much the output of a new time unit signal pulse should further be delayed in order to compensate for any remaining deviation;
- a coarse compensation circuit arranged to receive the integer part (K−1) of each new deviation compensating signal and for injecting or inhibiting a number of pulses of the reference time signal in the divider circuit for each time unit signal pulse, said number of pulses depending on said integer part of the deviation compensating signal;
- a fraction accumulation circuit arranged to receive, for each time unit signal pulse, a new fractional part (n) of the deviation compensating signal, and to compute iteratively a new accumulated fractional deviation compensating signal (nACC) by adding said new one of said fractional parts (n) of the deviation compensating signal to the previous accumulated fractional deviation compensating signal;
- a scale conversion circuit arranged to provide and refresh periodically a digital frequency ratio signal (M/P) representative of a ratio (fRC/fXT) of the frequency of the high frequency oscillator over the frequency of the crystal oscillator, and further arranged for generating a fractional inhibition command signal (nINT) by converting the accumulated deviation compensating signal (nACC) into a corresponding number of periods of the interpolation signal;
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- a variable delay circuit arranged to receive each new fractional inhibition command signal (nINT) and to delay the output of the next time unit signal pulse for the duration of a corresponding number of periods of the interpolation signal.