Phase interpolator having adaptively biased phase mixer

A method of operation in a phase interpolator, the phase interpolator comprising an adaptively biased phase mixer, phase control circuitry, and an adaptive bias generator, the method comprising:

• providing a system clock signal having a selected frequency;
• providing a plurality of phase input signals offset in phase from one another and having the selected frequency;
• the phase control circuitry receiving a phase selection signal representing a selected phase and generating a plurality of phase control signals corresponding to the selected phase;
• the adaptive bias generator generating an adaptive bias signal in response to at least one mixer operating condition;
• each of a plurality of buffer circuits of the adaptively biased phase mixer receiving one of the plurality of phase input signals and the adaptive bias signal, each buffer circuit comprising a plurality of mixing transistors defining mixing transistor circuitry and a plurality of bias transistors defining adjustable bias transistor circuitry, the plurality of mixing transistors comprising a first group of mixing transistors connected in series with each other, the plurality of bias transistors comprising a first group of bias transistors connected in series with each other, the first group of mixing transistors connected in series with the first group of bias transistors;
• the adjustable bias transistor circuitry directly receiving the adaptive bias signal from the adaptive bias generator and adjusting a bias current in response to the adaptive bias signal;
• and
• the mixing transistor circuitry generating an output phase signal having the selected phase in response to the bias current, the plurality of phase control signals, and the phase input signals.