Clock multiplier with dynamically tuned lock range
AssigneeRambus Inc.
InventorsYue Lu, Jared L. Zerbe
Life of this patent
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Abstract
A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies.
Claims20
A method of operation within an integrated circuit device, the method comprising:
- determining a frequency ratio between an input clock signal and a reference clock signal during a first interval;
- tuning a frequency-locking range of a frequency-multiplying oscillator to a frequency band indicated by the frequency ratio to bound an oscillating frequency of the input clock signal;
- and
- after tuning the frequency-locking range of the frequency-multiplying oscillator, enabling the frequency-multiplying oscillator to generate an output clock signal that is a frequency-multiple of the input clock signal.
An integrated circuit device comprising:
- a frequency comparator to determine a frequency ratio between an input clock signal and a reference clock signal during a first interval;
- a frequency-multiplying oscillator having a variable frequency-locking range;
- and
- control logic to (i) tune the variable frequency-locking range of the frequency-multiplying oscillator to a frequency band indicated by the frequency ratio to bound an oscillating frequency of the input clock signal, and (ii) enable the frequency-multiplying oscillator to generate an output clock signal that is a frequency-multiple of the input clock signal.
A machine readable medium that stores data representative of a circuit component comprising:
- a frequency comparator to determine a frequency ratio between an input clock signal and a reference clock signal during a first interval;
- a frequency-multiplying oscillator having a variable frequency-locking range;
- and
- control logic to (i) tune the variable frequency-locking range of the frequency-multiplying oscillator to a frequency band indicated by the frequency ratio to bound an oscillating frequency of the input clock signal, and (ii) enable the frequency-multiplying oscillator to generate an output clock signal that is a frequency-multiple of the input clock signal.
Dependencies are inferred from the claim text.