Sampling circuit and sampling method
AssigneeReatek Semiconductor Corp.
InventorsChing-Sheng Cheng, Hsu-Jung Tung
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Abstract
A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal.
Claims12
A sampling circuit, comprising:
- a first delay chain, for delaying an input signal according to an up signal and a down signal, to generate a first delay signal;
- a second delay chain, for delaying the first delay signal according to a preset delay value, to generate a second delay signal;
- and
- a half-speed binary-phase detector, for sampling a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate the up signal, the down signal, and an output signal according to a sampling result of the data signal.
A sampling method, comprising:
- delaying an input signal according to an up signal a down signal, so as to generate a first delay signal;
- delaying the first delay signal according to a preset delay value, so as to generate a second delay signal;
- and
- sampling, by a half-speed binary-phase detector, a data signal according to edge trigger of the first delay signal and that of the second delay signal, so as to generate output data, the up signal, and the down signal.
Dependencies are inferred from the claim text.