US 8,896,348 B2 · Semiconductor apparatus

Abstract

In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.

Claims20

Dependent claims

A device comprising:

first and second power lines;
first and second sense nodes;
a first circuit unit comprising:
first and second transistors complementary in conductivity type to each other and coupled to each other at the first sense node, and
third and fourth transistors complementary in conductivity type to each other and coupled to each other at the second sense node,
the first and second transistors receiving a first clock signal at control electrodes thereof, the third and fourth transistors receiving a second clock signal at control electrodes thereof, and the second clock signal being complementary in phase to the first clock signal,
a second circuit unit coupled between the first power line and the first circuit unit, and configured to respond to a third clock signal;
a third circuit unit coupled between the second power line and the first circuit unit, and configured to respond to a fourth clock signal that is complementary in phase to the third clock signal;
and
a fifth transistor coupled between the first and second sense nodes.

7 more elements

A device comprising:

first and second power lines;
first and second sense nodes;
an amplifier having input terminals respectively connected to the first and second sense nodes;
a first circuit unit comprising:
first and second transistors complementary in conductivity type to each other and coupled to each other at the first sense node, and
third and fourth transistors complementary in conductivity type to each other and coupled to each other at the second sense node,
the first and second transistors receiving a first clock signal at control electrodes thereof, the third and fourth transistors receiving a second clock signal at control electrodes thereof, and the second clock signal being complementary in phase to the first clock signal,
a second circuit unit coupled between the first power line and the first circuit unit, and configured to respond to a third clock signal;
a third circuit unit coupled between the second power line and the first circuit unit, and configured to respond to a fourth clock signal that is complementary in phase to the third clock signal;
and
a fifth transistor coupled between the first and second sense nodes.

8 more elements

A semiconductor apparatus, comprising:

a clock terminal to receive an external clock signal;
a DLL (Delay Locked Loop) circuit that generates an internal clock signal synchronized with the external clock signal;
and
an internal circuit that uses the internal clock signal to perform an operation synchronized with the external clock signal,
wherein the DLL circuit comprises a phase detection circuit comprising:
first and second power lines;
first and second sense nodes;
a first circuit unit comprising:
first and second transistors complementary in conductivity type to each other and coupled to each other at the first sense node;
and
third and fourth transistors complementary in conductivity type to each other and coupled to each other at the second sense node,
the first and second transistors receiving a first clock signal at control electrodes thereof, the third and fourth transistors receiving a second clock signal at control electrodes thereof, and the second clock signal being complementary in phase to the first clock signal,
a second circuit unit coupled between the first power line and the first circuit unit, and configured to respond to a third clock signal;
a third circuit unit coupled between the second power line and the first circuit unit, and configured to respond to a fourth clock signal that is complementary in phase to the third clock signal;
and
a fifth transistor coupled between the first and second sense nodes.

13 more elements

Dependencies are inferred from the claim text.

Semiconductor apparatus

Life of this patent

Semiconductor apparatus

Life of this patent

Abstract

Claims20