Synchronous input signal capture system
AssigneeHamilton Sundstrand Corporation
InventorDavid S. Harman
Life of this patent
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Abstract
A synchronous digital signal capture system includes a first flip-flop and a synchronization module. The first flip-flop receives a logic control signal and a first clock signal having a first frequency. The first flip-flop is configured to output a synchronized data signal based on the logic control, and generate a synchronous reset signal that is a logic inverse of the synchronized data signal generated at the data output. The synchronization module receives a primary data signal and is configured to generate the logic control signal based on the primary input signal, a second clock signal, and the synchronous reset signal such that the first flip-flop generates the synchronized signal.
Claims14
A synchronous digital signal capture system, comprising:
- a first flip-flop to receive a logic control signal and a first clock signal having a first frequency, the first flip-flop configured to output a synchronized data signal based on the logic control signal, and to generate a synchronous reset signal that is a logic inverse of the synchronized data signal;
- a synchronization module including an input to receive a primary data signal and an output in electrical communication with the first flip-flop, the synchronization module configured to generate the logic control signal based on the primary data signal, the synchronous reset signal and a second clock signal such that the first flip-flop generates the synchronized data signal.
A method of synchronously capturing a digital signal, the method comprising:
- receiving a logic control signal and a first clock signal having a first frequency;
- outputting a synchronized data signal based on the logic control signal;
- generating a synchronous reset signal that is a logic inverse of the synchronized data signal;
- receiving a primary data signal;
- and
- generating the logic control signal based on the primary data signal, the synchronous reset signal and a second clock signal, and generating the synchronized data signal in response to generating the logic control signal.
Dependencies are inferred from the claim text.