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US 8,896,126 B2Granted
Packaging DRAM and SOC in an IC package
AssigneeMarvell World Trade Ltd.
InventorSehat Setardja
Life of this patent
Estimating the term…
Abstract
An integrated circuit package includes a first memory die having a first set of connections, a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections, a first substrate having a first opening and a second opening, the first substrate having a third set of connections to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections to connect to the second set of connections of the second memory die via the second opening, and a second substrate having a first integrated circuit disposed thereon. The first substrate is connected to the second substrate with the first integrated circuit disposed between the first substrate and second substrate.
Claims18
An integrated circuit package comprising:
- a first memory die having a first set of connections;
- a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections;
- a first substrate having (i) a first opening between a first portion and a second portion of the first substrate and (ii) a second opening between the second portion and a third portion of the first substrate, the first substrate having a third set of connections on the first portion to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections on the third portion to connect to the second set of connections of the second memory die via the second opening, wherein the second portion of the first substrate includes no connections to (i) the first set of connections of the first memory die and (ii) the second set of connections of the second memory die;
- and
- a second substrate having a first integrated circuit disposed thereon,
- wherein the first substrate is connected to the second substrate using solder balls with the first integrated circuit disposed between the first substrate and second substrate.
3 more elements
An integrated circuit package comprising:
- a first memory die having a first set of connections;
- a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections;
- a first substrate having (i) a first opening between a first portion and a second portion of the first substrate and (ii) a second opening between the second portion and a third portion of the first substrate, the first substrate having a third set of connections on the first portion to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections on the third portion to connect to the second set of connections of the second memory die via the second opening, wherein the second portion of the first substrate includes no connections to (i) the first set of connections of the first memory die and (ii) the second set of connections of the second memory die;
- a second substrate having a first integrated circuit disposed thereon;
- wherein the first substrate is connected to the second substrate with the first integrated circuit disposed between the first substrate and second substrate;
- a third memory die having a fifth set of connections;
- a fourth memory die arranged adjacent to the third memory die, the fourth memory die having a sixth set of connections;
- and
- a third substrate having a third opening and a fourth opening, the third substrate having a seventh set of connections to connect to the fifth set of connections of the third memory die via the third opening and an eighth set of connections to connect to the sixth set of connections of the fourth memory die via the fourth opening.
6 more elements
An integrated circuit package comprising:
- a first memory die having a first set of connections;
- a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections;
- a first substrate having (i) a first opening between a first portion and a second portion of the first substrate and (ii) a second opening between the second portion and a third portion of the first substrate, wherein the first and second memory dies are mounted on a first surface of the first substrate, wherein the first substrate has a third set of connections on the first portion to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections on the third portion to connect to the second set of connections of the second memory die via the second opening, wherein the second portion of the first substrate includes no connections to (i) the first set of connections of the first memory die and (ii) the second set of connections of the second memory die, wherein the third and fourth sets of connections are located on a second surface of the first substrate, and wherein the second surface is opposite to the first surface;
- and
- a second substrate having a first integrated circuit disposed on a third surface of the second substrate, wherein the third surface is adjacent to the second surface,
- wherein the first substrate is connected to the second substrate with the first integrated circuit disposed between the first substrate and second substrate.
3 more elements
Dependencies are inferred from the claim text.