Chip assembly system
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorLaurent-Luc Chapelon
Life of this patent
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Abstract
An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride.
Claims6
An assembly of semiconductor wafers/chips wherein the adjacent surfaces of two wafers/chips (W1, W2) each comprise a silicon oxide layer having copper pads formed therein, wherein the silicon oxide layer is coated, outside of regions in which the copper pads are formed, with a silicon nitride or silicon carbon nitride layer thinner than the thickness of the copper pads, and wherein an external surface of the silicon nitride or silicon carbon nitride layer is substantially planar with an external surface of the pads.
Dependencies are inferred from the claim text.