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US 8,896,106 B2Granted
Semiconductor packages having multiple lead frames and methods of formation thereof
AssigneeInfineon Technologies AG
InventorsRalf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
Life of this patent
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Abstract
In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.
Claims20
A semiconductor package comprising:
- a first lead frame;
- a second lead frame, wherein the first lead frame is disposed over the second lead frame, and wherein the first lead frame comprises a die paddle and a plurality of leads;
- and
- a semiconductor chip disposed over the first lead frame, the semiconductor chip coupled to the plurality of leads, wherein the first lead frame is disposed between the semiconductor chip and the second lead frame, wherein the die paddle and at least one lead of the plurality of leads overlaps with and mechanically supports a major surface of the semiconductor chip, wherein the semiconductor chip comprises a transistor comprising a source region, a gate region, and a drain region, wherein the first lead frame comprises a die paddle coupled to the source region, and wherein the plurality of leads comprise a source lead coupled to the die paddle, a drain lead coupled to the drain region, and a gate lead coupled to the gate region.
1 more element
A semiconductor package comprising:
- a first lead frame comprising a first die paddle and a plurality of leads;
- a second lead frame having a second die paddle, wherein the first die paddle is disposed over the second die paddle;
- and
- a semiconductor chip disposed over the first die paddle, the semiconductor chip having a plurality of contact regions on a first side facing the first lead frame, the plurality of contact regions being coupled to the plurality of leads, wherein the first lead frame is disposed between the semiconductor chip and the second lead frame, wherein the first die paddle and at least one lead of the plurality of leads overlaps with and mechanically supports a major surface of the semiconductor chip, wherein the semiconductor chip comprises a transistor comprising a source region, a gate region, and a drain region, wherein the first die paddle is coupled to the source region, and wherein the plurality of leads comprise a source lead coupled to the second die paddle, a drain lead coupled to the drain region, and a gate lead coupled to the gate region.
1 more element
A semiconductor package comprising:
- a first lead frame comprising a first die paddle and a plurality of leads;
- a second lead frame having a second die paddle, the first die paddle disposed over the second die paddle;
- a semiconductor chip disposed over the first die paddle, the semiconductor chip having a plurality of contact regions on a first side facing the first lead frame, the plurality of contact regions being coupled to the plurality of leads, wherein the first lead frame is disposed between the semiconductor chip and the second lead frame, wherein the semiconductor chip has a second side opposite the first side, wherein the second side comprises a contact region, wherein the contact region on the second side is coupled to a lead of the plurality of leads of the first lead frame, and wherein the first die paddle and at least one lead of the plurality of leads overlaps with and mechanically supports a major surface of the semiconductor chip, wherein the semiconductor chip comprises a vertical transistor comprising a source region and a gate region on the first side, and a drain region on the second side, wherein the first die paddle is coupled to the source region, and wherein the plurality of leads comprise a source lead coupled to the second die paddle, a drain lead coupled to the drain region, and a gate lead coupled to the gate region;
- and
- an encapsulant disposed at the first lead frame, the second lead frame, and the semiconductor chip.
2 more elements
Dependencies are inferred from the claim text.