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US 8,896,087 B2Granted
Shallow trench isolation area having buried capacitor
AssigneeInfineon Technologies AG
InventorHartmud Terletzki
Life of this patent
Estimating the term…
Abstract
A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
Claims29
A semiconductor chip comprising:
- a substrate comprising a surface;
- an active transistor region having a body region and a substrate contact region disposed at the substrate, wherein the substrate contact region is coupled to the body region of the active transistor region, and wherein the substrate contact region forms a substrate contact to the body region of the active transistor region;
- a shallow trench isolation (STI) area disposed at the surface and disposed at least partially between the active transistor region and the substrate contact region;
- at least one capacitor at least partially buried in the isolation material of the STI area;
- and
- a STI disposed at the surface, wherein the substrate contact region coupled to the body region is disposed between the STI and the STI area comprising the at least one capacitor.
3 more elements
A semiconductor device comprising:
- a first shallow trench isolation (STI) disposed between an active transistor region having a body region and a substrate contact region of a semiconductor chip, wherein the substrate contact region is coupled to the body region of the active transistor region, the first STI comprising:
- an isolation trench formed into a surface of a substrate of the semiconductor chip, the isolation trench having sidewalls extending into the substrate;
- at least one capacitor which is at least partially buried in the isolation material of the first STI between the sidewalls;
- and
- a second STI disposed at the surface, wherein, along a direction perpendicular to the surface of the substrate and extending into the substrate, the second STI is shallower than the first STI, wherein the substrate contact region coupled to the body region is disposed between the second STI and the first STI comprising the at least one capacitor.
2 more elements
A semiconductor chip comprising:
- a well region disposed in a substrate, the well region having a first doping type;
- a first transistor disposed in the well region;
- a second transistor disposed in a region of the substrate having a second doping type adjacent the well region, the second doping type being opposite to the first doping type, wherein the first transistor is laterally adjacent to the second transistor along a lateral direction oriented along a major surface of the substrate;
- a first shallow trench isolation (STI) area comprising an opening disposed between the first transistor and the second transistor;
- and
- a first capacitor and a second capacitor disposed in the opening of the first STI area, the first capacitor having a bottom electrode and a top electrode, the second capacitor having a bottom electrode and a top electrode, wherein the first capacitor is disposed directly over the well region, and wherein the second capacitor is disposed over the region of the substrate having the second doping type and is laterally adjacent the well region along the lateral direction, and wherein, within the opening of the first STI area, along the lateral direction the bottom electrode of the first capacitor is laterally adjacent to the bottom electrode of the second capacitor, wherein the bottom electrode of the first capacitor is separated from the bottom electrode of the second capacitor by the isolating material of the first STI area.
3 more elements
Dependencies are inferred from the claim text.