Patterning embedded control lines for vertically stacked semiconductor elements

An apparatus comprising a multi-layer structure of semiconductor material formed by steps comprising:

• providing a first semiconductor wafer with a first facing surface on which a first conductive layer is formed, the first semiconductor wafer comprises an embedded silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor and a memory element layer is provided on the silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor and the memory element layer separates the first conductive layer from the silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor;
• attaching the first semiconductor wafer to a second semiconductor wafer to form the multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive layer is formed, wherein the first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure;
• and
• removing material from the first semiconductor wafer to form a plurality of spaced apart stacked pillars of semiconductor material and each pillar comprises a resistive random access memory element between the metal oxide semiconductor field effect transistor and the embedded combined conductive layer;
• thereafter
• removing portions of the embedded combined conductive layer to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure;
• and
• wherein the multi-wafer structure is characterized as a solid state memory comprising individual memory cells coupled to said plurality of control lines, wherein the individual memory cells are formed in the first semiconductor wafer after the spaced apart control lines are formed, and wherein control circuitry coupled to said memory elements is formed in the second semiconductor wafer prior to the formation of the spaced apart control lines.

An apparatus comprising a multi-layer structure of semiconductor material formed by steps comprising:

• providing a first semiconductor wafer with a first facing surface on which a first conductive layer is formed, the first semiconductor layer comprises an embedded silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor and a memory element layer is provided on the silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor and the memory element layer separates the first conductive layer from the silicon matrix of respectively doped regions corresponding to a metal oxide semiconductor field effect transistor;
• attaching the first semiconductor wafer to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive layer is formed, wherein the first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure;
• removing material from the first semiconductor wafer to form a plurality of spaced apart stacked pillars of semiconductor material and each pillar comprises a resistive random access memory element formed from the memory element layer between the metal oxide semiconductor field effect transistor and the embedded combined conductive layer;
• thereafter
• removing portions of the embedded combined conductive layer to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure, and wherein said control lines contact said resistive random access memory element and respective sets of the pillars are contactingly supported by the respective control lines and the resistive random access memory element is electrically between the metal oxide semiconductor field effect transistor and the control lines;
• and
• wherein the resistive random access memory element comprises a spin-torque transfer random access memory element;
• and
• wherein the multi-wafer structure is characterized as a solid state memory comprising individual memory cells coupled to said plurality of control lines, wherein the individual memory cells are formed in the first semiconductor wafer after the spaced apart control lines are formed, and wherein control circuitry coupled to said memory elements is formed in the second semiconductor wafer prior to the formation of the spaced apart control lines.